init
This commit is contained in:
commit
0b75add2d1
208
.clang-format
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208
.clang-format
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|
||||
---
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||||
Language: Cpp
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AlignOperands: Align
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AllowAllParametersOfDeclarationOnNextLine: true
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AllowShortEnumsOnASingleLine: true
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AllowShortBlocksOnASingleLine: Never
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AllowShortFunctionsOnASingleLine: All
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AllowShortLambdasOnASingleLine: All
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AllowShortIfStatementsOnASingleLine: WithoutElse
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AllowShortLoopsOnASingleLine: true
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AlwaysBreakAfterDefinitionReturnType: None
|
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AlwaysBreakAfterReturnType: None
|
||||
AlwaysBreakBeforeMultilineStrings: true
|
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AlwaysBreakTemplateDeclarations: Yes
|
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AttributeMacros:
|
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- __capability
|
||||
BinPackArguments: true
|
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BinPackParameters: true
|
||||
BraceWrapping:
|
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AfterCaseLabel: false
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AfterUnion: false
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AfterExternBlock: false
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BeforeElse: false
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BeforeLambdaBody: false
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BeforeWhile: false
|
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IndentBraces: false
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SplitEmptyFunction: true
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SplitEmptyRecord: true
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SplitEmptyNamespace: true
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BreakBeforeBinaryOperators: None
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BreakBeforeConceptDeclarations: true
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BreakBeforeBraces: Attach
|
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BreakBeforeInheritanceComma: false
|
||||
BreakInheritanceList: BeforeColon
|
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BreakBeforeTernaryOperators: true
|
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BreakConstructorInitializersBeforeComma: false
|
||||
BreakConstructorInitializers: BeforeColon
|
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BreakAfterJavaFieldAnnotations: false
|
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BreakStringLiterals: true
|
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ColumnLimit: 120
|
||||
CommentPragmas: '^ IWYU pragma:'
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CompactNamespaces: false
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ConstructorInitializerAllOnOneLineOrOnePerLine: true
|
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ConstructorInitializerIndentWidth: 4
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ContinuationIndentWidth: 4
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Cpp11BracedListStyle: true
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DisableFormat: false
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EmptyLineBeforeAccessModifier: LogicalBlock
|
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ExperimentalAutoDetectBinPacking: false
|
||||
FixNamespaceComments: true
|
||||
ForEachMacros:
|
||||
- foreach
|
||||
- Q_FOREACH
|
||||
- BOOST_FOREACH
|
||||
IfMacros:
|
||||
- KJ_IF_MAYBE
|
||||
IncludeBlocks: Regroup
|
||||
IncludeCategories:
|
||||
- Regex: '^[<"].*\.h[>"]'
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Priority: 0
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SortPriority: 0
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IncludeIsMainRegex: '([-_](test|unittest))?$'
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IndentGotoLabels: true
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|
||||
IndentExternBlock: AfterExternBlock
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||||
IndentRequires: false
|
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IndentWidth: 4
|
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IndentWrappedFunctionNames: false
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InsertTrailingCommas: None
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JavaScriptQuotes: Leave
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JavaScriptWrapImports: true
|
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KeepEmptyLinesAtTheStartOfBlocks: false
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LambdaBodyIndentation: Signature
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ObjCBinPackProtocolList: Never
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ObjCBlockIndentWidth: 2
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ObjCSpaceAfterProperty: false
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RawStringFormats:
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Delimiters:
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- cc
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- CC
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- cpp
|
||||
- Cpp
|
||||
- CPP
|
||||
- 'c++'
|
||||
- 'C++'
|
||||
CanonicalDelimiter: ''
|
||||
BasedOnStyle: google
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- Language: TextProto
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Delimiters:
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- pb
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- PB
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- proto
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- PROTO
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||||
EnclosingFunctions:
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||||
- EqualsProto
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||||
- EquivToProto
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||||
- PARSE_PARTIAL_TEXT_PROTO
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||||
- PARSE_TEST_PROTO
|
||||
- PARSE_TEXT_PROTO
|
||||
- ParseTextOrDie
|
||||
- ParseTextProtoOrDie
|
||||
- ParseTestProto
|
||||
- ParsePartialTestProto
|
||||
CanonicalDelimiter: pb
|
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BasedOnStyle: google
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ReferenceAlignment: Pointer
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ReflowComments: true
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ShortNamespaceLines: 1
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SpaceBeforeInheritanceColon: true
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SpaceBeforeParens: ControlStatements
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SpaceAroundPointerQualifiers: Default
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SpaceBeforeRangeBasedForLoopColon: true
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SpaceInEmptyBlock: false
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SpaceInEmptyParentheses: false
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SpacesBeforeTrailingComments: 2
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SpacesInAngles: Never
|
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SpacesInConditionalStatement: false
|
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SpacesInContainerLiterals: true
|
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SpacesInCStyleCastParentheses: false
|
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SpacesInLineCommentPrefix:
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SpacesInParentheses: false
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SpacesInSquareBrackets: false
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SpaceBeforeSquareBrackets: false
|
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BitFieldColonSpacing: Both
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Standard: Auto
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StatementAttributeLikeMacros:
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StatementMacros:
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- Q_UNUSED
|
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TabWidth: 8
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UseCRLF: false
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UseTab: Never
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- CF_SWIFT_NAME
|
||||
...
|
||||
|
||||
6
.gitignore
vendored
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6
.gitignore
vendored
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@ -0,0 +1,6 @@
|
||||
# settings
|
||||
.vscode
|
||||
|
||||
# build
|
||||
build/
|
||||
temp/
|
||||
46
Makefile
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46
Makefile
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@ -0,0 +1,46 @@
|
||||
# 目录定义
|
||||
DEPS_DIR = scripts
|
||||
BUILD_DIR = build
|
||||
|
||||
# 变量定义
|
||||
TARGET = firmware
|
||||
SOURCES = main.c src/*.c
|
||||
|
||||
# 编译选项
|
||||
CFLAGS ?= -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion \
|
||||
-Wformat-truncation -fno-common -Wconversion \
|
||||
-g3 -Og -ffunction-sections -fdata-sections \
|
||||
-Iinclude -mcpu=cortex-m0plus -mthumb -lm $(EXTRA_CFLAGS)
|
||||
LDFLAGS ?= -T $(DEPS_DIR)/link.ld -nostartfiles -nostdlib --specs nano.specs \
|
||||
-lc -lgcc -Wl,--gc-sections -Wl,-Map=$(BUILD_DIR)/$(TARGET).$@.map
|
||||
|
||||
# 命令定义
|
||||
ifeq ($(OS),Windows_NT)
|
||||
RM = cmd /C del /Q /F
|
||||
else
|
||||
RM = rm -f
|
||||
endif
|
||||
|
||||
# 目录创建
|
||||
$(shell if [ ! -e $(DEPS_DIR) ];then mkdir -p $(DEPS_DIR); fi)
|
||||
$(shell if [ ! -e $(BUILD_DIR) ];then mkdir -p $(BUILD_DIR); fi)
|
||||
|
||||
build: bin
|
||||
|
||||
elf: $(SOURCES)
|
||||
arm-none-eabi-gcc $(SOURCES) $(CFLAGS) $(LDFLAGS) -o $(BUILD_DIR)/$(TARGET).elf
|
||||
|
||||
bin: elf
|
||||
arm-none-eabi-objcopy -O binary $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).bin
|
||||
|
||||
flash: bin
|
||||
JLinkExe -device MKL25Z128XXX4 -if SWD -speed 4000 -autoconnect 1 -CommanderScript $(DEPS_DIR)/flash.jlink
|
||||
|
||||
disassembly: elf
|
||||
arm-none-eabi-objdump -D -S $(BUILD_DIR)/$(TARGET).elf > $(BUILD_DIR)/$(TARGET).S
|
||||
|
||||
disassembly-none: elf
|
||||
arm-none-eabi-objdump -D $(BUILD_DIR)/$(TARGET).elf > $(BUILD_DIR)/$(TARGET).S
|
||||
|
||||
clean:
|
||||
$(RM) $(BUILD_DIR)/$(TARGET).*
|
||||
5728
include/MKL25Z4.h
Normal file
5728
include/MKL25Z4.h
Normal file
File diff suppressed because it is too large
Load Diff
1202
include/cmsis_gcc.h
Normal file
1202
include/cmsis_gcc.h
Normal file
File diff suppressed because it is too large
Load Diff
855
include/core_cm0plus.h
Normal file
855
include/core_cm0plus.h
Normal file
@ -0,0 +1,855 @@
|
||||
/**************************************************************************/ /**
|
||||
* @file core_cm0plus.h
|
||||
* @brief CMSIS Cortex-M0+ Core
|
||||
*Peripheral Access Layer Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM0PLUS_H_GENERIC
|
||||
#define __CORE_CM0PLUS_H_GENERIC
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||
CMSIS violates the following MISRA-C:2004 rules:
|
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||
Function definitions in header files are used to allow 'inlining'.
|
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||
Unions are used for effective representation of core registers.
|
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||
Function-like macros are used to allow more efficient code.
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\ingroup Cortex-M0+
|
||||
@{
|
||||
*/
|
||||
|
||||
/* CMSIS CM0+ definitions */
|
||||
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
|
||||
#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
|
||||
#define __CM0PLUS_CMSIS_VERSION \
|
||||
((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
|
||||
|
||||
#define __CORTEX_M (0x00U) /*!< Cortex-M Core */
|
||||
|
||||
#if defined(__CC_ARM)
|
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||
#define __STATIC_INLINE static __inline
|
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||
#define __STATIC_INLINE static __inline
|
||||
|
||||
#elif defined(__GNUC__)
|
||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined(__ICCARM__)
|
||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined(__TMS470__)
|
||||
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined(__TASKING__)
|
||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined(__CSMC__)
|
||||
#define __packed
|
||||
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#else
|
||||
#error Unknown compiler
|
||||
#endif
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all
|
||||
*/
|
||||
#define __FPU_USED 0U
|
||||
|
||||
#if defined(__CC_ARM)
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_PCS_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined(__GNUC__)
|
||||
#if defined(__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined(__ICCARM__)
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined(__TMS470__)
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined(__TASKING__)
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined(__CSMC__)
|
||||
#if (__CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#include "core_cmFunc.h" /* Core Function Access */
|
||||
#include "core_cmInstr.h" /* Core Instruction Access */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0PLUS_H_GENERIC */
|
||||
|
||||
#ifndef __CMSIS_GENERIC
|
||||
|
||||
#ifndef __CORE_CM0PLUS_H_DEPENDANT
|
||||
#define __CORE_CM0PLUS_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __CM0PLUS_REV
|
||||
#define __CM0PLUS_REV 0x0000U
|
||||
#warning "__CM0PLUS_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __MPU_PRESENT
|
||||
#define __MPU_PRESENT 0U
|
||||
#warning "__MPU_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __VTOR_PRESENT
|
||||
#define __VTOR_PRESENT 0U
|
||||
#warning "__VTOR_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||
|
||||
<strong>IO Type Qualifiers</strong> are used
|
||||
\li to specify the access to peripheral variables.
|
||||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
||||
/* following defines should be used for structure members */
|
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||
|
||||
/*@} end of group Cortex-M0+ */
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction
|
||||
Core Register contain:
|
||||
- Core Register
|
||||
- Core NVIC Register
|
||||
- Core SCB Register
|
||||
- Core SysTick Register
|
||||
- Core MPU Register
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||
*/
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CORE Status and Control Registers
|
||||
\brief Core Register type definitions.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR).
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t _reserved0 : 28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C : 1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N : 1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
/* APSR Register Definitions */
|
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
/* IPSR Register Definitions */
|
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1 : 3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C : 1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N : 1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
/* xPSR Register Definitions */
|
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL).
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */
|
||||
uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1 : 30; /*!< bit: 2..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/* CONTROL Register Definitions */
|
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||
|
||||
#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
|
||||
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
|
||||
|
||||
/*@} end of group CMSIS_CORE */
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||
\brief Type definitions for the NVIC Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||
uint32_t RESERVED0[31U];
|
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||
uint32_t RSERVED1[31U];
|
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||
uint32_t RESERVED2[31U];
|
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31U];
|
||||
uint32_t RESERVED4[64U];
|
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||
\brief Type definitions for the System Control Block Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB).
|
||||
*/
|
||||
typedef struct {
|
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||
#if (__VTOR_PRESENT == 1U)
|
||||
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
|
||||
#else
|
||||
uint32_t RESERVED0;
|
||||
#endif
|
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED1;
|
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
#if (__VTOR_PRESENT == 1U)
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
|
||||
#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
|
||||
#endif
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCB */
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||
\brief Type definitions for the System Timer Registers.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick).
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||
|
||||
/*@} end of group CMSIS_SysTick */
|
||||
|
||||
#if (__MPU_PRESENT == 1U)
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
||||
\brief Type definitions for the Memory Protection Unit (MPU)
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Memory Protection Unit (MPU).
|
||||
*/
|
||||
typedef struct {
|
||||
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
|
||||
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
|
||||
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
|
||||
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
|
||||
} MPU_Type;
|
||||
|
||||
/* MPU Type Register Definitions */
|
||||
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
|
||||
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
|
||||
|
||||
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
|
||||
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
|
||||
|
||||
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
|
||||
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
|
||||
|
||||
/* MPU Control Register Definitions */
|
||||
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
|
||||
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
|
||||
|
||||
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
|
||||
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
|
||||
|
||||
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
|
||||
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
|
||||
|
||||
/* MPU Region Number Register Definitions */
|
||||
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
|
||||
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
|
||||
|
||||
/* MPU Region Base Address Register Definitions */
|
||||
#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
|
||||
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
|
||||
|
||||
#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
|
||||
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
|
||||
|
||||
#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
|
||||
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
|
||||
|
||||
/* MPU Region Attribute and Size Register Definitions */
|
||||
#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
|
||||
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
|
||||
|
||||
#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
|
||||
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
|
||||
|
||||
#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
|
||||
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
|
||||
|
||||
#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
|
||||
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
|
||||
|
||||
#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
|
||||
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
|
||||
|
||||
#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
|
||||
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
|
||||
|
||||
#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
|
||||
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
|
||||
|
||||
#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
|
||||
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
|
||||
|
||||
#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
|
||||
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
|
||||
|
||||
#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
|
||||
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
|
||||
|
||||
/*@} end of group CMSIS_MPU */
|
||||
#endif
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||
\brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via
|
||||
processor. Therefore they are not covered by the Cortex-M0+ header file.
|
||||
@{
|
||||
*/
|
||||
/*@} end of group CMSIS_CoreDebug */
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of the bit field.
|
||||
\return Masked and shifted value.
|
||||
*/
|
||||
#define _VAL2FLD(field, value) ((value << field##_Pos) & field##_Msk)
|
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of register.
|
||||
\return Masked and shifted bit field value.
|
||||
*/
|
||||
#define _FLD2VAL(field, value) ((value & field##_Msk) >> field##_Pos)
|
||||
|
||||
/*@} end of group CMSIS_core_bitfield */
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_base Core Definitions
|
||||
\brief Definitions for base addresses, unions, and structures.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Memory mapping of Cortex-M0+ Hardware */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
|
||||
#define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */
|
||||
|
||||
#if (__MPU_PRESENT == 1U)
|
||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
||||
#define MPU ((MPU_Type *)MPU_BASE) /*!< Memory Protection Unit */
|
||||
#endif
|
||||
|
||||
/*@} */
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
Core Function Interface contains:
|
||||
- Core NVIC Functions
|
||||
- Core SysTick Functions
|
||||
- Core Register Access Functions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||
*/
|
||||
|
||||
/* ########################## NVIC functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Interrupt Priorities are WORD accessible only under ARMv6M */
|
||||
/* The following MACROS handle generation of the register offset and byte masks */
|
||||
#define _BIT_SHIFT(IRQn) (((((uint32_t)(int32_t)(IRQn))) & 0x03UL) * 8UL)
|
||||
#define _SHP_IDX(IRQn) ((((((uint32_t)(int32_t)(IRQn)) & 0x0FUL) - 8UL) >> 2UL))
|
||||
#define _IP_IDX(IRQn) ((((uint32_t)(int32_t)(IRQn)) >> 2UL))
|
||||
|
||||
/**
|
||||
\brief Enable External Interrupt
|
||||
\details Enables a device-specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) {
|
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Disable External Interrupt
|
||||
\details Disables a device-specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) {
|
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt
|
||||
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return 0 Interrupt status is not pending.
|
||||
\return 1 Interrupt status is pending.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) {
|
||||
return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt
|
||||
\details Sets the pending bit of an external interrupt.
|
||||
\param [in] IRQn Interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) {
|
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt
|
||||
\details Clears the pending bit of an external interrupt.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) {
|
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority
|
||||
\details Sets the priority of an interrupt.
|
||||
\note The priority cannot be set for every core interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\param [in] priority Priority to set.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
|
||||
if ((int32_t)(IRQn) < 0) {
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
} else {
|
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority
|
||||
\details Reads the priority of an interrupt.
|
||||
The interrupt number can be positive to specify an external (device specific) interrupt,
|
||||
or negative to specify an internal (core) interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Interrupt Priority.
|
||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) {
|
||||
if ((int32_t)(IRQn) < 0) {
|
||||
return (
|
||||
(uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
} else {
|
||||
return (
|
||||
(uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
\brief System Reset
|
||||
\details Initiates a system reset request to reset the MCU.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SystemReset(void) {
|
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */
|
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for (;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */
|
||||
|
||||
/* ################################## SysTick function ############################################ */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||
\brief Functions that configure the System.
|
||||
@{
|
||||
*/
|
||||
|
||||
#if (__Vendor_SysTickConfig == 0U)
|
||||
|
||||
/**
|
||||
\brief System Tick Configuration
|
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
Counter is in free running mode to generate periodic interrupts.
|
||||
\param [in] ticks Number of ticks between two interrupts.
|
||||
\return 0 Function succeeded.
|
||||
\return 1 Function failed.
|
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||
must contain a vendor-specific implementation of this function.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
|
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
|
||||
return (1UL); /* Reload value impossible */
|
||||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||
return (0UL); /* Function successful */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0PLUS_H_DEPENDANT */
|
||||
|
||||
#endif /* __CMSIS_GENERIC */
|
||||
86
include/core_cmFunc.h
Normal file
86
include/core_cmFunc.h
Normal file
@ -0,0 +1,86 @@
|
||||
/**************************************************************************/ /**
|
||||
* @file core_cmFunc.h
|
||||
* @brief CMSIS Cortex-M Core Function
|
||||
*Access Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CMFUNC_H
|
||||
#define __CORE_CMFUNC_H
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/*------------------ RealView Compiler -----------------*/
|
||||
#if defined(__CC_ARM)
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
/*------------------ ARM Compiler V6 -------------------*/
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armcc_V6.h"
|
||||
|
||||
/*------------------ GNU Compiler ----------------------*/
|
||||
#elif defined(__GNUC__)
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
/*------------------ ICC Compiler ----------------------*/
|
||||
#elif defined(__ICCARM__)
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/
|
||||
#elif defined(__TMS470__)
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
/*------------------ TASKING Compiler ------------------*/
|
||||
#elif defined(__TASKING__)
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/
|
||||
#elif defined(__CSMC__)
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
#endif /* __CORE_CMFUNC_H */
|
||||
86
include/core_cmInstr.h
Normal file
86
include/core_cmInstr.h
Normal file
@ -0,0 +1,86 @@
|
||||
/**************************************************************************/ /**
|
||||
* @file core_cmInstr.h
|
||||
* @brief CMSIS Cortex-M Core
|
||||
*Instruction Access Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CMINSTR_H
|
||||
#define __CORE_CMINSTR_H
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/*------------------ RealView Compiler -----------------*/
|
||||
#if defined(__CC_ARM)
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
/*------------------ ARM Compiler V6 -------------------*/
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armcc_V6.h"
|
||||
|
||||
/*------------------ GNU Compiler ----------------------*/
|
||||
#elif defined(__GNUC__)
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
/*------------------ ICC Compiler ----------------------*/
|
||||
#elif defined(__ICCARM__)
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/
|
||||
#elif defined(__TMS470__)
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
/*------------------ TASKING Compiler ------------------*/
|
||||
#elif defined(__TASKING__)
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/
|
||||
#elif defined(__CSMC__)
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
#endif /* __CORE_CMINSTR_H */
|
||||
21
include/derivative.h
Normal file
21
include/derivative.h
Normal file
@ -0,0 +1,21 @@
|
||||
#pragma once
|
||||
|
||||
#include "MKL25Z4.h"
|
||||
|
||||
// Define Clock Settings
|
||||
|
||||
#define CORCLK_DEFAULT 20970000u // Default Core clock, 20.97 Mhz
|
||||
#define BUSCLK_DEFAULT 10500000u // Default Bus Rate clock, 10.5 Mhz, half of CORCLK
|
||||
|
||||
#define CPU_XTAL_CLK_HZ 8000000u // Value of the external crystal or oscillator clock frequency in Hz
|
||||
#define CPU_INT_SLOW_CLK_HZ 32768u // Value of the slow internal oscillator clock frequency in Hz
|
||||
#define CPU_INT_FAST_CLK_HZ 4000000u // Value of the fast internal oscillator clock frequency in Hz
|
||||
|
||||
#define UART_MSG UART1
|
||||
#define UART_WIFI UART2
|
||||
|
||||
#define PI 3.1415926
|
||||
#define BIT(x) (1UL << (x))
|
||||
|
||||
extern uint32_t CORCLK;
|
||||
extern uint32_t BUSCLK;
|
||||
34
include/systick.h
Normal file
34
include/systick.h
Normal file
@ -0,0 +1,34 @@
|
||||
#pragma once
|
||||
|
||||
#include "derivative.h"
|
||||
#include <stdbool.h>
|
||||
|
||||
extern volatile uint32_t ms_ticks;
|
||||
|
||||
static inline void spin(volatile uint32_t count) {
|
||||
if (count == 0) return;
|
||||
while (count--) asm("nop");
|
||||
}
|
||||
|
||||
static inline void systick_init(uint32_t ticks) {
|
||||
if ((ticks - 1) > 0xffffff) return; // Systick timer is 24 bit
|
||||
SysTick->LOAD = ticks - 1;
|
||||
SysTick->VAL = 0;
|
||||
SysTick->CTRL = SysTick_CTRL_ENABLE_Msk // Enable systick timer
|
||||
| SysTick_CTRL_TICKINT_Msk // Enable interrupt
|
||||
| SysTick_CTRL_CLKSOURCE_Msk; // Use butin-in clock
|
||||
}
|
||||
|
||||
// t: expiration time, prd: period
|
||||
static inline bool timer_expired(uint32_t *t, uint32_t prd) {
|
||||
if (ms_ticks + prd < *t) *t = 0; // Time wrapped? Reset timer
|
||||
if (*t == 0) *t = ms_ticks + prd; // First poll? Set expiration
|
||||
if (*t > ms_ticks) return false; // Not expired yet, return
|
||||
*t = (ms_ticks - *t) > prd ? ms_ticks + prd : *t + prd; // Next expiration time
|
||||
return true; // Expired, return true
|
||||
}
|
||||
|
||||
static inline void delay_ms(uint32_t ms) {
|
||||
uint32_t start = ms_ticks;
|
||||
while (ms_ticks - start < ms) asm("nop");
|
||||
}
|
||||
84
include/uart.h
Normal file
84
include/uart.h
Normal file
@ -0,0 +1,84 @@
|
||||
#pragma once
|
||||
|
||||
#include "derivative.h"
|
||||
#include "systick.h"
|
||||
#include <stdarg.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
static inline void uart_init(UART_Type *UART, unsigned long baud) {
|
||||
// Enable clock for UART and PORT, then set RXD, TXD
|
||||
if (UART == UART1) {
|
||||
SIM->SCGC4 |= SIM_SCGC4_UART1_MASK;
|
||||
SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK;
|
||||
|
||||
PORTC->PCR[3] = PORT_PCR_MUX(0x3);
|
||||
PORTC->PCR[4] = PORT_PCR_MUX(0x3);
|
||||
} else if (UART == UART2) {
|
||||
SIM->SCGC4 |= SIM_SCGC4_UART2_MASK;
|
||||
SIM->SCGC5 |= SIM_SCGC5_PORTE_MASK;
|
||||
|
||||
PORTE->PCR[23] = PORT_PCR_MUX(0x3);
|
||||
PORTE->PCR[22] = PORT_PCR_MUX(0x3);
|
||||
} else
|
||||
return;
|
||||
|
||||
// Make sure that the transmitter and receiver are disabled while we change settings.
|
||||
UART->C2 &= (uint8_t)(~(UART_C2_TE_MASK | UART_C2_RE_MASK));
|
||||
|
||||
// default settings, no parity, so entire register is cleared
|
||||
UART->C1 = 0x00;
|
||||
|
||||
// Buad = BUSCLK / (16 * SBR)
|
||||
unsigned short sbr = (unsigned short)(BUSCLK / (baud * 16));
|
||||
|
||||
// UARTx_BDH bits 0~4 is the high 5 bits of SBR (band rate)
|
||||
UART->BDH |= (sbr & (uint8_t)(UART_BDH_SBR_MASK << 8)) >> 8;
|
||||
// UARTx_BLH is the low 8 bits of SBR (band rate)
|
||||
UART->BDL = sbr & UART_BDL_SBR_MASK;
|
||||
// Enable receiver and transmitter
|
||||
UART->C2 |= UART_C2_TE_MASK // Transmitter enable
|
||||
| UART_C2_RE_MASK // Receiver enable
|
||||
| UART_C2_RIE_MASK; // Receiver interrupt enable
|
||||
}
|
||||
|
||||
static inline int uart_read_ready(UART_Type *UART) {
|
||||
// Receive Data Register Full Flag (RDRF): set when the receive data buffer is full
|
||||
return UART->S1 & UART_S1_RDRF_MASK;
|
||||
}
|
||||
|
||||
static inline uint8_t uart_read_byte(UART_Type *UART) { return (uint8_t)UART->D; }
|
||||
|
||||
static inline void uart_write_byte(UART_Type *UART, uint8_t byte) {
|
||||
// Transmit Data Register Empty Flag (TDRE): set when the transmit data buffer is empty
|
||||
while (!(UART->S1 & UART_S1_TDRE_MASK)) asm("nop");
|
||||
UART->D = byte;
|
||||
}
|
||||
|
||||
static inline void uart_write_buf(UART_Type *UART, char *buf, size_t len) {
|
||||
while (len-- > 0) uart_write_byte(UART, *(uint8_t *)buf++);
|
||||
}
|
||||
|
||||
static inline void uart_printf(UART_Type *UART, const char *format, ...) {
|
||||
va_list args;
|
||||
va_start(args, format);
|
||||
char buf[64];
|
||||
vsprintf(buf, format, args);
|
||||
uart_write_buf(UART, buf, strlen(buf));
|
||||
va_end(args);
|
||||
}
|
||||
|
||||
static inline size_t uart_getline(UART_Type *UART, char *buf) {
|
||||
size_t cnt = 0;
|
||||
while (1) {
|
||||
while (!uart_read_ready(UART)) asm("nop");
|
||||
*(uint8_t *)buf = (unsigned char)uart_read_byte(UART);
|
||||
cnt += 1;
|
||||
if (*(uint8_t *)buf == 0x0d) {
|
||||
*(uint8_t *)buf = 0x0a;
|
||||
break;
|
||||
}
|
||||
(uint8_t *)buf++;
|
||||
}
|
||||
return cnt;
|
||||
}
|
||||
22
main.c
Normal file
22
main.c
Normal file
@ -0,0 +1,22 @@
|
||||
#include "ESP8266.h"
|
||||
#include "derivative.h"
|
||||
#include "systick.h"
|
||||
#include "uart.h"
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
int main(void) {
|
||||
// Initialize
|
||||
systick_init(CORCLK / 1000); // Period of systick timer : 1ms
|
||||
uart_init(UART_MSG, 9600); // Initialize UART1 with PC
|
||||
|
||||
uart_printf(UART_MSG, "System Clock: %lu\r\n", CORCLK);
|
||||
uart_printf(UART_MSG, "Bus Clock: %lu\r\n", BUSCLK);
|
||||
|
||||
uint32_t timer = 0;
|
||||
for (;;) {
|
||||
if (timer_expired(&timer, 1000)) {
|
||||
uart_printf(UART_MSG, "LED: %d, tick: %lu\r\n", GPIOC->PDOR & BIT(12) ? 1 : 0, ms_ticks);
|
||||
}
|
||||
}
|
||||
}
|
||||
5
scripts/flash.jlink
Normal file
5
scripts/flash.jlink
Normal file
@ -0,0 +1,5 @@
|
||||
r
|
||||
unlock Kinetis
|
||||
loadbin build/firmware.bin, 0x0
|
||||
r
|
||||
q
|
||||
45
scripts/link.ld
Normal file
45
scripts/link.ld
Normal file
@ -0,0 +1,45 @@
|
||||
ENTRY(_reset);
|
||||
MEMORY {
|
||||
interrupt(rx) : ORIGIN = 0x00000000, LENGTH = 0xC0
|
||||
cfmprotrom(rx) : ORIGIN = 0x00000400, LENGTH = 0x10
|
||||
flash(rx) : ORIGIN = 0x00000410, LENGTH = 128K - 0x410
|
||||
sram(rwx) : ORIGIN = 0x1ffff000, LENGTH = 16K
|
||||
}
|
||||
|
||||
_estack = ORIGIN(sram) + LENGTH(sram); /* 0x20003000, the end of sRAM */
|
||||
|
||||
SECTIONS {
|
||||
/* vector table */
|
||||
.vectors : {
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.vectors));
|
||||
. = ALIGN(4);
|
||||
} > interrupt
|
||||
/* Flash Configuration Field (FCF) */
|
||||
.cfmprotect :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.cfmconfig))
|
||||
. = ALIGN(4);
|
||||
} > cfmprotrom
|
||||
|
||||
.text : { *(.text*) } > flash /* firmware code */
|
||||
.rodata : { *(.rodata*) } > flash /* read-only data */
|
||||
|
||||
/* use _sada and _edata in _reset() to copy data to sRAM */
|
||||
.data : {
|
||||
_sdata = .; /* start of .data section */
|
||||
*(.first_data)
|
||||
*(.data SORT(.data.*))
|
||||
_edata = .; /* end of .data section */
|
||||
} > sram AT > flash
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
.bss : {
|
||||
_sbss = .; /* start of .bss section */
|
||||
*(.bss SORT(.bss.*) COMMON)
|
||||
_ebss = .; /* end of .bss section */
|
||||
} > sram
|
||||
|
||||
_end = .;
|
||||
}
|
||||
9
src/derivative.c
Normal file
9
src/derivative.c
Normal file
@ -0,0 +1,9 @@
|
||||
#include "derivative.h"
|
||||
|
||||
uint32_t CORCLK = CORCLK_DEFAULT;
|
||||
uint32_t BUSCLK = BUSCLK_DEFAULT;
|
||||
|
||||
// ms count, volatile is important!!
|
||||
volatile uint32_t ms_ticks;
|
||||
|
||||
void SysTick_Handler(void) { ms_ticks++; }
|
||||
205
src/startup.c
Normal file
205
src/startup.c
Normal file
@ -0,0 +1,205 @@
|
||||
#include "derivative.h"
|
||||
#include <string.h>
|
||||
|
||||
extern int main(void); // Defined in main.c
|
||||
|
||||
static void __init_hardware() {
|
||||
// Switch off watchdog
|
||||
SIM->COPC = 0x0;
|
||||
}
|
||||
|
||||
static void zero_fill_bss(void) {
|
||||
extern char _sbss[];
|
||||
extern char _ebss[];
|
||||
memset(_sbss, 0, (size_t)(_ebss - _sbss));
|
||||
}
|
||||
|
||||
static void copy_data(void) {
|
||||
extern char _sdata[];
|
||||
extern char _edata[];
|
||||
extern char _sidata[];
|
||||
memcpy(_sdata, _sidata, (size_t)(_edata - _sdata));
|
||||
}
|
||||
|
||||
uint32_t MCGOUTClock;
|
||||
uint16_t Divider;
|
||||
|
||||
static void FLL_clock(void) {
|
||||
/*
|
||||
FRDIV: FLL External Reference Divider, bits 3-5 of MCG_C1
|
||||
0b000 - 0b101: Divide Factor is 2^FRDIV
|
||||
110: Divide Factor is 1280
|
||||
111: Divide Factor is 1536
|
||||
|
||||
IREFS: Internal Reference Select, bit 2 of MCG_C1
|
||||
0: External reference clock is selected.
|
||||
1: The slow internal reference clock is selected.
|
||||
|
||||
RANGE0: Frequency Range Select, bit 4-5 of MCG_C2
|
||||
00: Low frequency range selected for the crystal oscillator.
|
||||
01: High frequency range selected for the crystal oscillator.
|
||||
1x: Very high frequency range selected for the crystal oscillator.
|
||||
*/
|
||||
// FLL reference clock
|
||||
if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
|
||||
if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
|
||||
case 0x38U:
|
||||
Divider = 1536U;
|
||||
break;
|
||||
case 0x30U:
|
||||
Divider = 1280U;
|
||||
break;
|
||||
default:
|
||||
Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
|
||||
break;
|
||||
}
|
||||
else
|
||||
Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
|
||||
|
||||
MCGOUTClock = (CPU_XTAL_CLK_HZ / Divider);
|
||||
} else
|
||||
MCGOUTClock = CPU_INT_SLOW_CLK_HZ;
|
||||
|
||||
/*
|
||||
DMX32: DCO Maximum Frequency with 32.768 kHz Reference, bit 7 of MCG_C4
|
||||
DRST_DRS: DCO Range Select, bits 5-6 of MCG_C4
|
||||
*/
|
||||
switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
|
||||
case 0x00U:
|
||||
MCGOUTClock *= 640U;
|
||||
break;
|
||||
case 0x20U:
|
||||
MCGOUTClock *= 1280U;
|
||||
break;
|
||||
case 0x40U:
|
||||
MCGOUTClock *= 1920U;
|
||||
break;
|
||||
case 0x60U:
|
||||
MCGOUTClock *= 2560U;
|
||||
break;
|
||||
case 0x80U:
|
||||
MCGOUTClock *= 732U;
|
||||
break;
|
||||
case 0xA0U:
|
||||
MCGOUTClock *= 1464U;
|
||||
break;
|
||||
case 0xC0U:
|
||||
MCGOUTClock *= 2197U;
|
||||
break;
|
||||
case 0xE0U:
|
||||
MCGOUTClock *= 2929U;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void PLL_clock(void) {
|
||||
/*
|
||||
PRDIV0: PLL External Reference Divider, bits 0-4 of MCG_C5
|
||||
value from 00000 to 11000, divide Factor from 1 to 25
|
||||
|
||||
VDIV0: VCO 0 Divider, bits 0-4 of MCG_C6
|
||||
value from 00000 to 11111, multiply Factor from 24 to 55
|
||||
*/
|
||||
Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 1U);
|
||||
MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider);
|
||||
Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
|
||||
MCGOUTClock *= Divider;
|
||||
}
|
||||
|
||||
static void inter_clock(void) {
|
||||
/*
|
||||
IRCS: Internal Reference Clock Select, bit 0 of MCG_C2
|
||||
0: Slow internal reference clock selected.
|
||||
1: Fast internal reference clock selected.
|
||||
|
||||
FCRDIV: Fast Clock Internal Reference Divider, bits 1-3 of MCG_SC
|
||||
0b000 - 0b111: Divide Factor is 2^FCRDIV
|
||||
*/
|
||||
if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)
|
||||
MCGOUTClock = CPU_INT_SLOW_CLK_HZ;
|
||||
else {
|
||||
Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
|
||||
MCGOUTClock = (uint32_t)(CPU_INT_FAST_CLK_HZ / Divider);
|
||||
}
|
||||
}
|
||||
|
||||
static void exter_clock(void) { MCGOUTClock = CPU_XTAL_CLK_HZ; }
|
||||
|
||||
static void clock_init(void) {
|
||||
/*
|
||||
CLKS: Clock Source Select, bits 6-7 of MCG_C1
|
||||
00: Output of FLL or PLL is selected (depends on PLLS control bit).
|
||||
01: Internal reference clock is selected.
|
||||
10: External reference clock is selected.
|
||||
|
||||
PLLS: PLL Select, bit 4 of MCG_C6
|
||||
0: FLL is selected.
|
||||
1: PLL is selected. (PRDIV0 must be programmed so divider can generate a PLL reference clock)
|
||||
|
||||
OUTDIV1: Clock 1 Output Divider, bits 28-31 of SIM_CLKDIV1
|
||||
value from 0b0000 to 0b1111, divide factor from 1 to 16
|
||||
|
||||
OUTDIV4: Clock 4 Output Divider, bits 16-18 of SIM_CLKDIV1
|
||||
value from 0b000 to 0b111, divide factor from 1 to 8, default 0b001 (2)
|
||||
*/
|
||||
if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
|
||||
if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)
|
||||
FLL_clock();
|
||||
else
|
||||
PLL_clock();
|
||||
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U)
|
||||
inter_clock();
|
||||
else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)
|
||||
exter_clock();
|
||||
|
||||
CORCLK = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
|
||||
CORCLK = (uint32_t)(CORCLK / 1000U) * 1000U;
|
||||
BUSCLK = CORCLK / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT));
|
||||
BUSCLK = (uint32_t)(BUSCLK / 1000U) * 1000U;
|
||||
}
|
||||
|
||||
__attribute__((naked, noreturn)) void _reset(void) {
|
||||
__init_hardware();
|
||||
zero_fill_bss();
|
||||
copy_data();
|
||||
clock_init();
|
||||
|
||||
main();
|
||||
for (;;) (void)0;
|
||||
}
|
||||
|
||||
// Interrupt service routine (ISR)
|
||||
extern void _estack(void); // Defined in link.ld
|
||||
extern void SysTick_Handler(void); // Defined in main.c
|
||||
|
||||
void Default_Handler() { __asm("bkpt"); }
|
||||
|
||||
/*
|
||||
Set tab (the vector table) in the section ".vectors"
|
||||
and the size of the vector table is 16 + 32
|
||||
the first 16 * 4 bytes are reserved for the Cortex-M0+ core
|
||||
the first one is the initial stack pointer
|
||||
the second one is the initial program counter
|
||||
*/
|
||||
__attribute__((section(".vectors"))) void (*tab[16 + 32])(void) = {
|
||||
_estack, // Initial stack pointer
|
||||
_reset, // Reset handler
|
||||
Default_Handler, // NMI handler
|
||||
Default_Handler, // Hard Fault handler
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
Default_Handler, // SVC handler
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
Default_Handler, // PendSV handler
|
||||
SysTick_Handler // SysTick handler
|
||||
};
|
||||
|
||||
__attribute__((section(".cfmconfig"))) uint32_t(cfm[4]) = {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFE};
|
||||
12
src/syscalls.c
Normal file
12
src/syscalls.c
Normal file
@ -0,0 +1,12 @@
|
||||
#include <sys/types.h>
|
||||
|
||||
extern char _end;
|
||||
|
||||
void *_sbrk(int incr) {
|
||||
static unsigned char *heap = NULL;
|
||||
unsigned char *prev_heap;
|
||||
if (heap == NULL) heap = (unsigned char *)&_end;
|
||||
prev_heap = heap;
|
||||
heap += incr;
|
||||
return prev_heap;
|
||||
}
|
||||
Reference in New Issue
Block a user