2023-04-17 21:56:42 +08:00
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#pragma once
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#include "derivative.h"
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#include "systick.h"
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#include <stdarg.h>
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#include <stdio.h>
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#include <string.h>
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static inline void uart_init(UART_Type *UART, unsigned long baud) {
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// Enable clock for UART and PORT, then set RXD, TXD
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if (UART == UART1) {
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SIM->SCGC4 |= SIM_SCGC4_UART1_MASK;
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SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK;
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PORTC->PCR[3] = PORT_PCR_MUX(0x3);
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PORTC->PCR[4] = PORT_PCR_MUX(0x3);
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} else if (UART == UART2) {
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SIM->SCGC4 |= SIM_SCGC4_UART2_MASK;
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SIM->SCGC5 |= SIM_SCGC5_PORTE_MASK;
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PORTE->PCR[23] = PORT_PCR_MUX(0x3);
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PORTE->PCR[22] = PORT_PCR_MUX(0x3);
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2023-04-24 01:05:42 +08:00
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} else return;
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2023-04-17 21:56:42 +08:00
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// Make sure that the transmitter and receiver are disabled while we change settings.
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UART->C2 &= (uint8_t)(~(UART_C2_TE_MASK | UART_C2_RE_MASK));
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// default settings, no parity, so entire register is cleared
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UART->C1 = 0x00;
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// Buad = BUSCLK / (16 * SBR)
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unsigned short sbr = (unsigned short)(BUSCLK / (baud * 16));
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// UARTx_BDH bits 0~4 is the high 5 bits of SBR (band rate)
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UART->BDH |= (sbr & (uint8_t)(UART_BDH_SBR_MASK << 8)) >> 8;
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// UARTx_BLH is the low 8 bits of SBR (band rate)
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UART->BDL = sbr & UART_BDL_SBR_MASK;
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// Enable receiver and transmitter
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2023-04-17 22:45:13 +08:00
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UART->C2 |= UART_C2_TE_MASK // Transmitter enable
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| UART_C2_RE_MASK; // Receiver enable
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}
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static inline void uart_rie_enable(UART_Type *UART) {
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2023-04-19 18:15:42 +08:00
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// Enable UART interrupt
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2023-04-24 01:05:42 +08:00
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if (UART == UART1) NVIC_EnableIRQ(UART1_IRQn);
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else if (UART == UART2) NVIC_EnableIRQ(UART2_IRQn);
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2023-04-17 22:45:13 +08:00
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UART->C2 |= UART_C2_RIE_MASK; // Receiver interrupt enable
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2023-04-17 21:56:42 +08:00
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}
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static inline int uart_read_ready(UART_Type *UART) {
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// Receive Data Register Full Flag (RDRF): set when the receive data buffer is full
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return UART->S1 & UART_S1_RDRF_MASK;
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}
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static inline uint8_t uart_read_byte(UART_Type *UART) { return (uint8_t)UART->D; }
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static inline void uart_write_byte(UART_Type *UART, uint8_t byte) {
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// Transmit Data Register Empty Flag (TDRE): set when the transmit data buffer is empty
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while (!(UART->S1 & UART_S1_TDRE_MASK)) asm("nop");
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UART->D = byte;
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}
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static inline void uart_write_buf(UART_Type *UART, char *buf, size_t len) {
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while (len-- > 0) uart_write_byte(UART, *(uint8_t *)buf++);
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}
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static inline void uart_printf(UART_Type *UART, const char *format, ...) {
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va_list args;
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va_start(args, format);
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char buf[64];
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vsprintf(buf, format, args);
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uart_write_buf(UART, buf, strlen(buf));
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va_end(args);
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}
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static inline size_t uart_getline(UART_Type *UART, char *buf) {
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size_t cnt = 0;
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while (1) {
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while (!uart_read_ready(UART)) asm("nop");
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*(uint8_t *)buf = (unsigned char)uart_read_byte(UART);
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cnt += 1;
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2023-04-19 18:15:42 +08:00
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if (*(uint8_t *)buf == 0x0a) break;
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2023-04-17 21:56:42 +08:00
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(uint8_t *)buf++;
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}
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return cnt;
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}
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2023-04-28 16:20:46 +08:00
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static inline void string_format(char *buf, const char *format, ...) {
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va_list args;
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va_start(args, format);
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vsprintf(buf, format, args);
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}
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