5729 lines
253 KiB
C
5729 lines
253 KiB
C
/*
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** ###################################################################
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** Processors: MKL25Z128VFM4
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** MKL25Z128VFT4
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** MKL25Z128VLH4
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** MKL25Z128VLK4
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** MKL25Z32VFM4
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** MKL25Z32VFT4
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** MKL25Z32VLH4
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** MKL25Z32VLK4
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** MKL25Z64VFM4
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** MKL25Z64VFT4
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** MKL25Z64VLH4
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** MKL25Z64VLK4
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**
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** Compilers: Keil ARM C/C++ Compiler
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** Freescale C/C++ for Embedded ARM
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** GNU C Compiler
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** IAR ANSI C/C++ Compiler for ARM
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** MCUXpresso Compiler
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**
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** Reference manual: KL25P80M48SF0RM, Rev.3, Sep 2012
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** Version: rev. 2.5, 2015-02-19
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** Build: b170112
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**
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** Abstract:
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** CMSIS Peripheral Access Layer for MKL25Z4
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**
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** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc.
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** Copyright 2016 - 2017 NXP
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** Redistribution and use in source and binary forms, with or without modification,
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** are permitted provided that the following conditions are met:
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**
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** o Redistributions of source code must retain the above copyright notice, this list
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** of conditions and the following disclaimer.
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**
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** o Redistributions in binary form must reproduce the above copyright notice, this
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** list of conditions and the following disclaimer in the documentation and/or
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** other materials provided with the distribution.
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**
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** o Neither the name of the copyright holder nor the names of its
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** contributors may be used to endorse or promote products derived from this
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** software without specific prior written permission.
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**
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** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**
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** http: www.nxp.com
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** mail: support@nxp.com
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**
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** Revisions:
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** - rev. 1.0 (2012-06-13)
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** Initial version.
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** - rev. 1.1 (2012-06-21)
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** Update according to reference manual rev. 1.
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** - rev. 1.2 (2012-08-01)
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** Device type UARTLP changed to UART0.
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** - rev. 1.3 (2012-10-04)
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** Update according to reference manual rev. 3.
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** - rev. 1.4 (2012-11-22)
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** MCG module - bit LOLS in MCG_S register renamed to LOLS0.
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** NV registers - bit EZPORT_DIS in NV_FOPT register removed.
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** - rev. 1.5 (2013-04-05)
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** Changed start of doxygen comment.
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** - rev. 2.0 (2013-10-29)
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** Register accessor macros added to the memory map.
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** Symbols for Processor Expert memory map compatibility added to the memory map.
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** Startup file for gcc has been updated according to CMSIS 3.2.
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** System initialization updated.
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** - rev. 2.1 (2014-07-16)
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** Module access macro module_BASES replaced by module_BASE_PTRS.
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** System initialization and startup updated.
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** - rev. 2.2 (2014-08-22)
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** System initialization updated - default clock config changed.
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** - rev. 2.3 (2014-08-28)
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** Update of startup files - possibility to override DefaultISR added.
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** - rev. 2.4 (2014-10-14)
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** Interrupt INT_LPTimer renamed to INT_LPTMR0.
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** - rev. 2.5 (2015-02-19)
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** Renamed interrupt vector LLW to LLWU.
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**
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** ###################################################################
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*/
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/*!
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* @file MKL25Z4.h
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* @version 2.5
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* @date 2015-02-19
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* @brief CMSIS Peripheral Access Layer for MKL25Z4
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*
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* CMSIS Peripheral Access Layer for MKL25Z4
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*/
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#ifndef _MKL25Z4_H_
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#define _MKL25Z4_H_ /**< Symbol preventing repeated inclusion */
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/** Memory map major version (memory maps with equal major version number are
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* compatible) */
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#define MCU_MEM_MAP_VERSION 0x0200U
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/** Memory map minor version */
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#define MCU_MEM_MAP_VERSION_MINOR 0x0005U
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/* ----------------------------------------------------------------------------
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-- Interrupt vector numbers
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup Interrupt_vector_numbers Interrupt vector numbers
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* @{
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*/
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/** Interrupt Number Definitions */
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#define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */
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typedef enum IRQn {
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/* Auxiliary constants */
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NotAvail_IRQn = -128, /**< Not available device specific interrupt */
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/* Core interrupts */
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NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
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HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
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SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
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PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
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SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
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/* Device specific interrupts */
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DMA0_IRQn = 0, /**< DMA channel 0 transfer complete */
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DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */
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DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */
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DMA3_IRQn = 3, /**< DMA channel 3 transfer complete */
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Reserved20_IRQn = 4, /**< Reserved interrupt */
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FTFA_IRQn = 5, /**< Command complete and read collision */
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LVD_LVW_IRQn = 6, /**< Low-voltage detect, low-voltage warning */
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LLWU_IRQn = 7, /**< Low leakage wakeup Unit */
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I2C0_IRQn = 8, /**< I2C0 interrupt */
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I2C1_IRQn = 9, /**< I2C1 interrupt */
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SPI0_IRQn = 10, /**< SPI0 single interrupt vector for all sources */
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SPI1_IRQn = 11, /**< SPI1 single interrupt vector for all sources */
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UART0_IRQn = 12, /**< UART0 status and error */
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UART1_IRQn = 13, /**< UART1 status and error */
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UART2_IRQn = 14, /**< UART2 status and error */
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ADC0_IRQn = 15, /**< ADC0 interrupt */
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CMP0_IRQn = 16, /**< CMP0 interrupt */
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TPM0_IRQn = 17, /**< TPM0 single interrupt vector for all sources */
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TPM1_IRQn = 18, /**< TPM1 single interrupt vector for all sources */
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TPM2_IRQn = 19, /**< TPM2 single interrupt vector for all sources */
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RTC_IRQn = 20, /**< RTC alarm */
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RTC_Seconds_IRQn = 21, /**< RTC seconds */
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PIT_IRQn = 22, /**< PIT interrupt */
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Reserved39_IRQn = 23, /**< Reserved interrupt */
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USB0_IRQn = 24, /**< USB0 interrupt */
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DAC0_IRQn = 25, /**< DAC0 interrupt */
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TSI0_IRQn = 26, /**< TSI0 interrupt */
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MCG_IRQn = 27, /**< MCG interrupt */
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LPTMR0_IRQn = 28, /**< LPTMR0 interrupt */
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Reserved45_IRQn = 29, /**< Reserved interrupt */
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PORTA_IRQn = 30, /**< PORTA Pin detect */
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PORTD_IRQn = 31 /**< PORTD Pin detect */
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} IRQn_Type;
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/*!
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* @}
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*/ /* end of group Interrupt_vector_numbers */
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/* ----------------------------------------------------------------------------
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-- Cortex M0 Core Configuration
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
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* @{
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*/
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#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
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#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
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#define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */
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#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
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#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
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#include "core_cm0plus.h" /* Core Peripheral Access Layer */
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/*!
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* @}
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*/ /* end of group Cortex_Core_Configuration */
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/* ----------------------------------------------------------------------------
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-- Mapping Information
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup Mapping_Information Mapping Information
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* @{
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*/
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/** Mapping Information */
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/*!
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* @addtogroup edma_request
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*!
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* @brief Structure for the DMA hardware request
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*
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* Defines the structure for the DMA hardware request collections. The user can configure the
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* hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
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* of the hardware request varies according to the to SoC.
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*/
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typedef enum _dma_request_source {
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kDmaRequestMux0Disable = 0 | 0x100U, /**< DMAMUX TriggerDisabled. */
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kDmaRequestMux0Reserved1 = 1 | 0x100U, /**< Reserved1 */
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kDmaRequestMux0UART0Rx = 2 | 0x100U, /**< UART0 Receive. */
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kDmaRequestMux0LPSCI0Rx = 2 | 0x100U, /**< UART0 Receive. */
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kDmaRequestMux0UART0Tx = 3 | 0x100U, /**< UART0 Transmit. */
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kDmaRequestMux0LPSCI0Tx = 3 | 0x100U, /**< UART0 Transmit. */
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kDmaRequestMux0UART1Rx = 4 | 0x100U, /**< UART1 Receive. */
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kDmaRequestMux0UART1Tx = 5 | 0x100U, /**< UART1 Transmit. */
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kDmaRequestMux0UART2Rx = 6 | 0x100U, /**< UART2 Receive. */
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kDmaRequestMux0UART2Tx = 7 | 0x100U, /**< UART2 Transmit. */
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kDmaRequestMux0Reserved8 = 8 | 0x100U, /**< Reserved8 */
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kDmaRequestMux0Reserved9 = 9 | 0x100U, /**< Reserved9 */
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kDmaRequestMux0Reserved10 = 10 | 0x100U, /**< Reserved10 */
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kDmaRequestMux0Reserved11 = 11 | 0x100U, /**< Reserved11 */
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kDmaRequestMux0Reserved12 = 12 | 0x100U, /**< Reserved12 */
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kDmaRequestMux0Reserved13 = 13 | 0x100U, /**< Reserved13 */
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kDmaRequestMux0Reserved14 = 14 | 0x100U, /**< Reserved14 */
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kDmaRequestMux0Reserved15 = 15 | 0x100U, /**< Reserved15 */
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kDmaRequestMux0SPI0Rx = 16 | 0x100U, /**< SPI0 Receive. */
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kDmaRequestMux0SPI0Tx = 17 | 0x100U, /**< SPI0 Transmit. */
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kDmaRequestMux0SPI1Rx = 18 | 0x100U, /**< SPI1 Receive. */
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kDmaRequestMux0SPI1Tx = 19 | 0x100U, /**< SPI1 Transmit. */
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kDmaRequestMux0Reserved20 = 20 | 0x100U, /**< Reserved20 */
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kDmaRequestMux0Reserved21 = 21 | 0x100U, /**< Reserved21 */
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kDmaRequestMux0I2C0 = 22 | 0x100U, /**< I2C0. */
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kDmaRequestMux0I2C1 = 23 | 0x100U, /**< I2C1. */
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kDmaRequestMux0TPM0Channel0 = 24 | 0x100U, /**< TPM0 C0V. */
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kDmaRequestMux0TPM0Channel1 = 25 | 0x100U, /**< TPM0 C1V. */
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kDmaRequestMux0TPM0Channel2 = 26 | 0x100U, /**< TPM0 C2V. */
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kDmaRequestMux0TPM0Channel3 = 27 | 0x100U, /**< TPM0 C3V. */
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kDmaRequestMux0TPM0Channel4 = 28 | 0x100U, /**< TPM0 C4V. */
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kDmaRequestMux0TPM0Channel5 = 29 | 0x100U, /**< TPM0 C5V. */
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kDmaRequestMux0Reserved30 = 30 | 0x100U, /**< Reserved30 */
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kDmaRequestMux0Reserved31 = 31 | 0x100U, /**< Reserved31 */
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kDmaRequestMux0TPM1Channel0 = 32 | 0x100U, /**< TPM1 C0V. */
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kDmaRequestMux0TPM1Channel1 = 33 | 0x100U, /**< TPM1 C1V. */
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kDmaRequestMux0TPM2Channel0 = 34 | 0x100U, /**< TPM2 C0V. */
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kDmaRequestMux0TPM2Channel1 = 35 | 0x100U, /**< TPM2 C1V. */
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kDmaRequestMux0Reserved36 = 36 | 0x100U, /**< Reserved36 */
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kDmaRequestMux0Reserved37 = 37 | 0x100U, /**< Reserved37 */
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kDmaRequestMux0Reserved38 = 38 | 0x100U, /**< Reserved38 */
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kDmaRequestMux0Reserved39 = 39 | 0x100U, /**< Reserved39 */
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kDmaRequestMux0ADC0 = 40 | 0x100U, /**< ADC0. */
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kDmaRequestMux0Reserved41 = 41 | 0x100U, /**< Reserved41 */
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kDmaRequestMux0CMP0 = 42 | 0x100U, /**< CMP0. */
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kDmaRequestMux0Reserved43 = 43 | 0x100U, /**< Reserved43 */
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kDmaRequestMux0Reserved44 = 44 | 0x100U, /**< Reserved44 */
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kDmaRequestMux0DAC0 = 45 | 0x100U, /**< DAC0. */
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kDmaRequestMux0Reserved46 = 46 | 0x100U, /**< Reserved46 */
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kDmaRequestMux0Reserved47 = 47 | 0x100U, /**< Reserved47 */
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kDmaRequestMux0Reserved48 = 48 | 0x100U, /**< Reserved48 */
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kDmaRequestMux0PortA = 49 | 0x100U, /**< PTA. */
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kDmaRequestMux0Reserved50 = 50 | 0x100U, /**< Reserved50 */
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kDmaRequestMux0Reserved51 = 51 | 0x100U, /**< Reserved51 */
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kDmaRequestMux0PortD = 52 | 0x100U, /**< PTD. */
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kDmaRequestMux0Reserved53 = 53 | 0x100U, /**< Reserved53 */
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kDmaRequestMux0TPM0Overflow = 54 | 0x100U, /**< TPM0. */
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kDmaRequestMux0TPM1Overflow = 55 | 0x100U, /**< TPM1. */
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kDmaRequestMux0TPM2Overflow = 56 | 0x100U, /**< TPM2. */
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kDmaRequestMux0TSI0 = 57 | 0x100U, /**< TSI0. */
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kDmaRequestMux0Reserved58 = 58 | 0x100U, /**< Reserved58 */
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kDmaRequestMux0Reserved59 = 59 | 0x100U, /**< Reserved59 */
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kDmaRequestMux0AlwaysOn60 = 60 | 0x100U, /**< DMAMUX Always Enabled slot. */
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kDmaRequestMux0AlwaysOn61 = 61 | 0x100U, /**< DMAMUX Always Enabled slot. */
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kDmaRequestMux0AlwaysOn62 = 62 | 0x100U, /**< DMAMUX Always Enabled slot. */
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kDmaRequestMux0AlwaysOn63 = 63 | 0x100U, /**< DMAMUX Always Enabled slot. */
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} dma_request_source_t;
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/* @} */
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/*!
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* @}
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*/ /* end of group Mapping_Information */
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/* ----------------------------------------------------------------------------
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-- Device Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup Peripheral_access_layer Device Peripheral Access Layer
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* @{
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*/
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/*
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** Start of section using anonymous unions
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*/
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#if defined(__ARMCC_VERSION)
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#pragma push
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#pragma anon_unions
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#elif defined(__CWCC__)
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#pragma push
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#pragma cpp_extensions on
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#elif defined(__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined(__IAR_SYSTEMS_ICC__)
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#pragma language = extended
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#else
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#error Not supported compiler type
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#endif
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/* ----------------------------------------------------------------------------
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-- ADC Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
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* @{
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*/
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/** ADC - Register Layout Typedef */
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typedef struct {
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__IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
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__IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
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__IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
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__I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
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__IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
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__IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
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__IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
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__IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
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__IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
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__IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
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__IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
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__IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
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__IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
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__IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
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__IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
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__IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
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__IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
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__IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
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uint8_t RESERVED_0[4];
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__IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
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__IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
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__IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
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__IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
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__IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
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__IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
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__IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
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} ADC_Type;
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/* ----------------------------------------------------------------------------
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-- ADC Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup ADC_Register_Masks ADC Register Masks
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* @{
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*/
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/*! @name SC1 - ADC Status and Control Registers 1 */
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#define ADC_SC1_ADCH_MASK (0x1FU)
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#define ADC_SC1_ADCH_SHIFT (0U)
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#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
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#define ADC_SC1_DIFF_MASK (0x20U)
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#define ADC_SC1_DIFF_SHIFT (5U)
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#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
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#define ADC_SC1_AIEN_MASK (0x40U)
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#define ADC_SC1_AIEN_SHIFT (6U)
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#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
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#define ADC_SC1_COCO_MASK (0x80U)
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#define ADC_SC1_COCO_SHIFT (7U)
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#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
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/* The count of ADC_SC1 */
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#define ADC_SC1_COUNT (2U)
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/*! @name CFG1 - ADC Configuration Register 1 */
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#define ADC_CFG1_ADICLK_MASK (0x3U)
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#define ADC_CFG1_ADICLK_SHIFT (0U)
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#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
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#define ADC_CFG1_MODE_MASK (0xCU)
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#define ADC_CFG1_MODE_SHIFT (2U)
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#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
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#define ADC_CFG1_ADLSMP_MASK (0x10U)
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#define ADC_CFG1_ADLSMP_SHIFT (4U)
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#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
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#define ADC_CFG1_ADIV_MASK (0x60U)
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#define ADC_CFG1_ADIV_SHIFT (5U)
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#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
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#define ADC_CFG1_ADLPC_MASK (0x80U)
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#define ADC_CFG1_ADLPC_SHIFT (7U)
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#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
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/*! @name CFG2 - ADC Configuration Register 2 */
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#define ADC_CFG2_ADLSTS_MASK (0x3U)
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#define ADC_CFG2_ADLSTS_SHIFT (0U)
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#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
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#define ADC_CFG2_ADHSC_MASK (0x4U)
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#define ADC_CFG2_ADHSC_SHIFT (2U)
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#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
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#define ADC_CFG2_ADACKEN_MASK (0x8U)
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#define ADC_CFG2_ADACKEN_SHIFT (3U)
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#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
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#define ADC_CFG2_MUXSEL_MASK (0x10U)
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#define ADC_CFG2_MUXSEL_SHIFT (4U)
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#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
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/*! @name R - ADC Data Result Register */
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#define ADC_R_D_MASK (0xFFFFU)
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#define ADC_R_D_SHIFT (0U)
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#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
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/* The count of ADC_R */
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#define ADC_R_COUNT (2U)
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/*! @name CV1 - Compare Value Registers */
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#define ADC_CV1_CV_MASK (0xFFFFU)
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#define ADC_CV1_CV_SHIFT (0U)
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#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
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/*! @name CV2 - Compare Value Registers */
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#define ADC_CV2_CV_MASK (0xFFFFU)
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#define ADC_CV2_CV_SHIFT (0U)
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#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
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/*! @name SC2 - Status and Control Register 2 */
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#define ADC_SC2_REFSEL_MASK (0x3U)
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#define ADC_SC2_REFSEL_SHIFT (0U)
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#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
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#define ADC_SC2_DMAEN_MASK (0x4U)
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#define ADC_SC2_DMAEN_SHIFT (2U)
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#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
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#define ADC_SC2_ACREN_MASK (0x8U)
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#define ADC_SC2_ACREN_SHIFT (3U)
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#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
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#define ADC_SC2_ACFGT_MASK (0x10U)
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#define ADC_SC2_ACFGT_SHIFT (4U)
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#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
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#define ADC_SC2_ACFE_MASK (0x20U)
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#define ADC_SC2_ACFE_SHIFT (5U)
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#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
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#define ADC_SC2_ADTRG_MASK (0x40U)
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#define ADC_SC2_ADTRG_SHIFT (6U)
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#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
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#define ADC_SC2_ADACT_MASK (0x80U)
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#define ADC_SC2_ADACT_SHIFT (7U)
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#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
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/*! @name SC3 - Status and Control Register 3 */
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#define ADC_SC3_AVGS_MASK (0x3U)
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#define ADC_SC3_AVGS_SHIFT (0U)
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#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
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#define ADC_SC3_AVGE_MASK (0x4U)
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#define ADC_SC3_AVGE_SHIFT (2U)
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#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
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#define ADC_SC3_ADCO_MASK (0x8U)
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#define ADC_SC3_ADCO_SHIFT (3U)
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#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
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#define ADC_SC3_CALF_MASK (0x40U)
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#define ADC_SC3_CALF_SHIFT (6U)
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#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
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#define ADC_SC3_CAL_MASK (0x80U)
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#define ADC_SC3_CAL_SHIFT (7U)
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#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
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/*! @name OFS - ADC Offset Correction Register */
|
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#define ADC_OFS_OFS_MASK (0xFFFFU)
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#define ADC_OFS_OFS_SHIFT (0U)
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#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
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/*! @name PG - ADC Plus-Side Gain Register */
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#define ADC_PG_PG_MASK (0xFFFFU)
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#define ADC_PG_PG_SHIFT (0U)
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#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
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/*! @name MG - ADC Minus-Side Gain Register */
|
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#define ADC_MG_MG_MASK (0xFFFFU)
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#define ADC_MG_MG_SHIFT (0U)
|
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#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
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/*! @name CLPD - ADC Plus-Side General Calibration Value Register */
|
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#define ADC_CLPD_CLPD_MASK (0x3FU)
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#define ADC_CLPD_CLPD_SHIFT (0U)
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#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
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/*! @name CLPS - ADC Plus-Side General Calibration Value Register */
|
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#define ADC_CLPS_CLPS_MASK (0x3FU)
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#define ADC_CLPS_CLPS_SHIFT (0U)
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#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
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/*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
|
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#define ADC_CLP4_CLP4_MASK (0x3FFU)
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#define ADC_CLP4_CLP4_SHIFT (0U)
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#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
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/*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
|
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#define ADC_CLP3_CLP3_MASK (0x1FFU)
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#define ADC_CLP3_CLP3_SHIFT (0U)
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#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
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/*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
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#define ADC_CLP2_CLP2_MASK (0xFFU)
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#define ADC_CLP2_CLP2_SHIFT (0U)
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#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
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/*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
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#define ADC_CLP1_CLP1_MASK (0x7FU)
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#define ADC_CLP1_CLP1_SHIFT (0U)
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#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
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/*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
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#define ADC_CLP0_CLP0_MASK (0x3FU)
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#define ADC_CLP0_CLP0_SHIFT (0U)
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#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
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/*! @name CLMD - ADC Minus-Side General Calibration Value Register */
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#define ADC_CLMD_CLMD_MASK (0x3FU)
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#define ADC_CLMD_CLMD_SHIFT (0U)
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#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
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/*! @name CLMS - ADC Minus-Side General Calibration Value Register */
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#define ADC_CLMS_CLMS_MASK (0x3FU)
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#define ADC_CLMS_CLMS_SHIFT (0U)
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#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
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/*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
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#define ADC_CLM4_CLM4_MASK (0x3FFU)
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#define ADC_CLM4_CLM4_SHIFT (0U)
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#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
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/*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
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#define ADC_CLM3_CLM3_MASK (0x1FFU)
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#define ADC_CLM3_CLM3_SHIFT (0U)
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#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
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/*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
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#define ADC_CLM2_CLM2_MASK (0xFFU)
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#define ADC_CLM2_CLM2_SHIFT (0U)
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#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
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/*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
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#define ADC_CLM1_CLM1_MASK (0x7FU)
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#define ADC_CLM1_CLM1_SHIFT (0U)
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#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
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/*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
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#define ADC_CLM0_CLM0_MASK (0x3FU)
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#define ADC_CLM0_CLM0_SHIFT (0U)
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#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
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/*!
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* @}
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*/ /* end of group ADC_Register_Masks */
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/* ADC - Peripheral instance base addresses */
|
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/** Peripheral ADC0 base address */
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#define ADC0_BASE (0x4003B000u)
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/** Peripheral ADC0 base pointer */
|
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#define ADC0 ((ADC_Type *)ADC0_BASE)
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/** Array initializer of ADC peripheral base addresses */
|
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#define ADC_BASE_ADDRS \
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{ ADC0_BASE }
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/** Array initializer of ADC peripheral base pointers */
|
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#define ADC_BASE_PTRS \
|
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{ ADC0 }
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/** Interrupt vectors for the ADC peripheral type */
|
|
#define ADC_IRQS \
|
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{ ADC0_IRQn }
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|
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/*!
|
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* @}
|
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*/ /* end of group ADC_Peripheral_Access_Layer */
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|
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/* ----------------------------------------------------------------------------
|
|
-- CMP Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
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|
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/*!
|
|
* @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
|
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* @{
|
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*/
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|
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/** CMP - Register Layout Typedef */
|
|
typedef struct {
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__IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
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__IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
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__IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
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__IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
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|
__IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
|
|
__IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
|
|
} CMP_Type;
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|
|
/* ----------------------------------------------------------------------------
|
|
-- CMP Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup CMP_Register_Masks CMP Register Masks
|
|
* @{
|
|
*/
|
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|
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/*! @name CR0 - CMP Control Register 0 */
|
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#define CMP_CR0_HYSTCTR_MASK (0x3U)
|
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#define CMP_CR0_HYSTCTR_SHIFT (0U)
|
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#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
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#define CMP_CR0_FILTER_CNT_MASK (0x70U)
|
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#define CMP_CR0_FILTER_CNT_SHIFT (4U)
|
|
#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
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|
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/*! @name CR1 - CMP Control Register 1 */
|
|
#define CMP_CR1_EN_MASK (0x1U)
|
|
#define CMP_CR1_EN_SHIFT (0U)
|
|
#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
|
|
#define CMP_CR1_OPE_MASK (0x2U)
|
|
#define CMP_CR1_OPE_SHIFT (1U)
|
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#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
|
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#define CMP_CR1_COS_MASK (0x4U)
|
|
#define CMP_CR1_COS_SHIFT (2U)
|
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#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
|
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#define CMP_CR1_INV_MASK (0x8U)
|
|
#define CMP_CR1_INV_SHIFT (3U)
|
|
#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
|
|
#define CMP_CR1_PMODE_MASK (0x10U)
|
|
#define CMP_CR1_PMODE_SHIFT (4U)
|
|
#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
|
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#define CMP_CR1_TRIGM_MASK (0x20U)
|
|
#define CMP_CR1_TRIGM_SHIFT (5U)
|
|
#define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
|
|
#define CMP_CR1_WE_MASK (0x40U)
|
|
#define CMP_CR1_WE_SHIFT (6U)
|
|
#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
|
|
#define CMP_CR1_SE_MASK (0x80U)
|
|
#define CMP_CR1_SE_SHIFT (7U)
|
|
#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
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|
|
|
/*! @name FPR - CMP Filter Period Register */
|
|
#define CMP_FPR_FILT_PER_MASK (0xFFU)
|
|
#define CMP_FPR_FILT_PER_SHIFT (0U)
|
|
#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
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|
|
|
/*! @name SCR - CMP Status and Control Register */
|
|
#define CMP_SCR_COUT_MASK (0x1U)
|
|
#define CMP_SCR_COUT_SHIFT (0U)
|
|
#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
|
|
#define CMP_SCR_CFF_MASK (0x2U)
|
|
#define CMP_SCR_CFF_SHIFT (1U)
|
|
#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
|
|
#define CMP_SCR_CFR_MASK (0x4U)
|
|
#define CMP_SCR_CFR_SHIFT (2U)
|
|
#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
|
|
#define CMP_SCR_IEF_MASK (0x8U)
|
|
#define CMP_SCR_IEF_SHIFT (3U)
|
|
#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
|
|
#define CMP_SCR_IER_MASK (0x10U)
|
|
#define CMP_SCR_IER_SHIFT (4U)
|
|
#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
|
|
#define CMP_SCR_DMAEN_MASK (0x40U)
|
|
#define CMP_SCR_DMAEN_SHIFT (6U)
|
|
#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
|
|
|
|
/*! @name DACCR - DAC Control Register */
|
|
#define CMP_DACCR_VOSEL_MASK (0x3FU)
|
|
#define CMP_DACCR_VOSEL_SHIFT (0U)
|
|
#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
|
|
#define CMP_DACCR_VRSEL_MASK (0x40U)
|
|
#define CMP_DACCR_VRSEL_SHIFT (6U)
|
|
#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
|
|
#define CMP_DACCR_DACEN_MASK (0x80U)
|
|
#define CMP_DACCR_DACEN_SHIFT (7U)
|
|
#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
|
|
|
|
/*! @name MUXCR - MUX Control Register */
|
|
#define CMP_MUXCR_MSEL_MASK (0x7U)
|
|
#define CMP_MUXCR_MSEL_SHIFT (0U)
|
|
#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
|
|
#define CMP_MUXCR_PSEL_MASK (0x38U)
|
|
#define CMP_MUXCR_PSEL_SHIFT (3U)
|
|
#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
|
|
#define CMP_MUXCR_PSTM_MASK (0x80U)
|
|
#define CMP_MUXCR_PSTM_SHIFT (7U)
|
|
#define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group CMP_Register_Masks */
|
|
|
|
/* CMP - Peripheral instance base addresses */
|
|
/** Peripheral CMP0 base address */
|
|
#define CMP0_BASE (0x40073000u)
|
|
/** Peripheral CMP0 base pointer */
|
|
#define CMP0 ((CMP_Type *)CMP0_BASE)
|
|
/** Array initializer of CMP peripheral base addresses */
|
|
#define CMP_BASE_ADDRS \
|
|
{ CMP0_BASE }
|
|
/** Array initializer of CMP peripheral base pointers */
|
|
#define CMP_BASE_PTRS \
|
|
{ CMP0 }
|
|
/** Interrupt vectors for the CMP peripheral type */
|
|
#define CMP_IRQS \
|
|
{ CMP0_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group CMP_Peripheral_Access_Layer */
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- DAC Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** DAC - Register Layout Typedef */
|
|
typedef struct {
|
|
struct { /* offset: 0x0, array step: 0x2 */
|
|
__IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
|
|
__IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
|
|
} DAT[2];
|
|
uint8_t RESERVED_0[28];
|
|
__IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
|
|
__IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
|
|
__IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
|
|
__IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
|
|
} DAC_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- DAC Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup DAC_Register_Masks DAC Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name DATL - DAC Data Low Register */
|
|
#define DAC_DATL_DATA0_MASK (0xFFU)
|
|
#define DAC_DATL_DATA0_SHIFT (0U)
|
|
#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
|
|
|
|
/* The count of DAC_DATL */
|
|
#define DAC_DATL_COUNT (2U)
|
|
|
|
/*! @name DATH - DAC Data High Register */
|
|
#define DAC_DATH_DATA1_MASK (0xFU)
|
|
#define DAC_DATH_DATA1_SHIFT (0U)
|
|
#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
|
|
|
|
/* The count of DAC_DATH */
|
|
#define DAC_DATH_COUNT (2U)
|
|
|
|
/*! @name SR - DAC Status Register */
|
|
#define DAC_SR_DACBFRPBF_MASK (0x1U)
|
|
#define DAC_SR_DACBFRPBF_SHIFT (0U)
|
|
#define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
|
|
#define DAC_SR_DACBFRPTF_MASK (0x2U)
|
|
#define DAC_SR_DACBFRPTF_SHIFT (1U)
|
|
#define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
|
|
|
|
/*! @name C0 - DAC Control Register */
|
|
#define DAC_C0_DACBBIEN_MASK (0x1U)
|
|
#define DAC_C0_DACBBIEN_SHIFT (0U)
|
|
#define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
|
|
#define DAC_C0_DACBTIEN_MASK (0x2U)
|
|
#define DAC_C0_DACBTIEN_SHIFT (1U)
|
|
#define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
|
|
#define DAC_C0_LPEN_MASK (0x8U)
|
|
#define DAC_C0_LPEN_SHIFT (3U)
|
|
#define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
|
|
#define DAC_C0_DACSWTRG_MASK (0x10U)
|
|
#define DAC_C0_DACSWTRG_SHIFT (4U)
|
|
#define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
|
|
#define DAC_C0_DACTRGSEL_MASK (0x20U)
|
|
#define DAC_C0_DACTRGSEL_SHIFT (5U)
|
|
#define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
|
|
#define DAC_C0_DACRFS_MASK (0x40U)
|
|
#define DAC_C0_DACRFS_SHIFT (6U)
|
|
#define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
|
|
#define DAC_C0_DACEN_MASK (0x80U)
|
|
#define DAC_C0_DACEN_SHIFT (7U)
|
|
#define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
|
|
|
|
/*! @name C1 - DAC Control Register 1 */
|
|
#define DAC_C1_DACBFEN_MASK (0x1U)
|
|
#define DAC_C1_DACBFEN_SHIFT (0U)
|
|
#define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
|
|
#define DAC_C1_DACBFMD_MASK (0x4U)
|
|
#define DAC_C1_DACBFMD_SHIFT (2U)
|
|
#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
|
|
#define DAC_C1_DMAEN_MASK (0x80U)
|
|
#define DAC_C1_DMAEN_SHIFT (7U)
|
|
#define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
|
|
|
|
/*! @name C2 - DAC Control Register 2 */
|
|
#define DAC_C2_DACBFUP_MASK (0x1U)
|
|
#define DAC_C2_DACBFUP_SHIFT (0U)
|
|
#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
|
|
#define DAC_C2_DACBFRP_MASK (0x10U)
|
|
#define DAC_C2_DACBFRP_SHIFT (4U)
|
|
#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group DAC_Register_Masks */
|
|
|
|
/* DAC - Peripheral instance base addresses */
|
|
/** Peripheral DAC0 base address */
|
|
#define DAC0_BASE (0x4003F000u)
|
|
/** Peripheral DAC0 base pointer */
|
|
#define DAC0 ((DAC_Type *)DAC0_BASE)
|
|
/** Array initializer of DAC peripheral base addresses */
|
|
#define DAC_BASE_ADDRS \
|
|
{ DAC0_BASE }
|
|
/** Array initializer of DAC peripheral base pointers */
|
|
#define DAC_BASE_PTRS \
|
|
{ DAC0 }
|
|
/** Interrupt vectors for the DAC peripheral type */
|
|
#define DAC_IRQS \
|
|
{ DAC0_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group DAC_Peripheral_Access_Layer */
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- DMA Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** DMA - Register Layout Typedef */
|
|
typedef struct {
|
|
uint8_t RESERVED_0[256];
|
|
struct { /* offset: 0x100, array step: 0x10 */
|
|
__IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
|
|
__IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
|
|
union { /* offset: 0x108, array step: 0x10 */
|
|
__IO uint32_t
|
|
DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
|
|
struct { /* offset: 0x108, array step: 0x10 */
|
|
uint8_t RESERVED_0[3];
|
|
__IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
|
|
} DMA_DSR_ACCESS8BIT;
|
|
};
|
|
__IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
|
|
} DMA[4];
|
|
} DMA_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- DMA Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup DMA_Register_Masks DMA Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name SAR - Source Address Register */
|
|
#define DMA_SAR_SAR_MASK (0xFFFFFFFFU)
|
|
#define DMA_SAR_SAR_SHIFT (0U)
|
|
#define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SAR_SAR_SHIFT)) & DMA_SAR_SAR_MASK)
|
|
|
|
/* The count of DMA_SAR */
|
|
#define DMA_SAR_COUNT (4U)
|
|
|
|
/*! @name DAR - Destination Address Register */
|
|
#define DMA_DAR_DAR_MASK (0xFFFFFFFFU)
|
|
#define DMA_DAR_DAR_SHIFT (0U)
|
|
#define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DAR_DAR_SHIFT)) & DMA_DAR_DAR_MASK)
|
|
|
|
/* The count of DMA_DAR */
|
|
#define DMA_DAR_COUNT (4U)
|
|
|
|
/*! @name DSR_BCR - DMA Status Register / Byte Count Register */
|
|
#define DMA_DSR_BCR_BCR_MASK (0xFFFFFFU)
|
|
#define DMA_DSR_BCR_BCR_SHIFT (0U)
|
|
#define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BCR_SHIFT)) & DMA_DSR_BCR_BCR_MASK)
|
|
#define DMA_DSR_BCR_DONE_MASK (0x1000000U)
|
|
#define DMA_DSR_BCR_DONE_SHIFT (24U)
|
|
#define DMA_DSR_BCR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_DONE_SHIFT)) & DMA_DSR_BCR_DONE_MASK)
|
|
#define DMA_DSR_BCR_BSY_MASK (0x2000000U)
|
|
#define DMA_DSR_BCR_BSY_SHIFT (25U)
|
|
#define DMA_DSR_BCR_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BSY_SHIFT)) & DMA_DSR_BCR_BSY_MASK)
|
|
#define DMA_DSR_BCR_REQ_MASK (0x4000000U)
|
|
#define DMA_DSR_BCR_REQ_SHIFT (26U)
|
|
#define DMA_DSR_BCR_REQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_REQ_SHIFT)) & DMA_DSR_BCR_REQ_MASK)
|
|
#define DMA_DSR_BCR_BED_MASK (0x10000000U)
|
|
#define DMA_DSR_BCR_BED_SHIFT (28U)
|
|
#define DMA_DSR_BCR_BED(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BED_SHIFT)) & DMA_DSR_BCR_BED_MASK)
|
|
#define DMA_DSR_BCR_BES_MASK (0x20000000U)
|
|
#define DMA_DSR_BCR_BES_SHIFT (29U)
|
|
#define DMA_DSR_BCR_BES(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BES_SHIFT)) & DMA_DSR_BCR_BES_MASK)
|
|
#define DMA_DSR_BCR_CE_MASK (0x40000000U)
|
|
#define DMA_DSR_BCR_CE_SHIFT (30U)
|
|
#define DMA_DSR_BCR_CE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_CE_SHIFT)) & DMA_DSR_BCR_CE_MASK)
|
|
|
|
/* The count of DMA_DSR_BCR */
|
|
#define DMA_DSR_BCR_COUNT (4U)
|
|
|
|
/* The count of DMA_DSR */
|
|
#define DMA_DSR_COUNT (4U)
|
|
|
|
/*! @name DCR - DMA Control Register */
|
|
#define DMA_DCR_LCH2_MASK (0x3U)
|
|
#define DMA_DCR_LCH2_SHIFT (0U)
|
|
#define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LCH2_SHIFT)) & DMA_DCR_LCH2_MASK)
|
|
#define DMA_DCR_LCH1_MASK (0xCU)
|
|
#define DMA_DCR_LCH1_SHIFT (2U)
|
|
#define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LCH1_SHIFT)) & DMA_DCR_LCH1_MASK)
|
|
#define DMA_DCR_LINKCC_MASK (0x30U)
|
|
#define DMA_DCR_LINKCC_SHIFT (4U)
|
|
#define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LINKCC_SHIFT)) & DMA_DCR_LINKCC_MASK)
|
|
#define DMA_DCR_D_REQ_MASK (0x80U)
|
|
#define DMA_DCR_D_REQ_SHIFT (7U)
|
|
#define DMA_DCR_D_REQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_D_REQ_SHIFT)) & DMA_DCR_D_REQ_MASK)
|
|
#define DMA_DCR_DMOD_MASK (0xF00U)
|
|
#define DMA_DCR_DMOD_SHIFT (8U)
|
|
#define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DMOD_SHIFT)) & DMA_DCR_DMOD_MASK)
|
|
#define DMA_DCR_SMOD_MASK (0xF000U)
|
|
#define DMA_DCR_SMOD_SHIFT (12U)
|
|
#define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SMOD_SHIFT)) & DMA_DCR_SMOD_MASK)
|
|
#define DMA_DCR_START_MASK (0x10000U)
|
|
#define DMA_DCR_START_SHIFT (16U)
|
|
#define DMA_DCR_START(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_START_SHIFT)) & DMA_DCR_START_MASK)
|
|
#define DMA_DCR_DSIZE_MASK (0x60000U)
|
|
#define DMA_DCR_DSIZE_SHIFT (17U)
|
|
#define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DSIZE_SHIFT)) & DMA_DCR_DSIZE_MASK)
|
|
#define DMA_DCR_DINC_MASK (0x80000U)
|
|
#define DMA_DCR_DINC_SHIFT (19U)
|
|
#define DMA_DCR_DINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DINC_SHIFT)) & DMA_DCR_DINC_MASK)
|
|
#define DMA_DCR_SSIZE_MASK (0x300000U)
|
|
#define DMA_DCR_SSIZE_SHIFT (20U)
|
|
#define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SSIZE_SHIFT)) & DMA_DCR_SSIZE_MASK)
|
|
#define DMA_DCR_SINC_MASK (0x400000U)
|
|
#define DMA_DCR_SINC_SHIFT (22U)
|
|
#define DMA_DCR_SINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SINC_SHIFT)) & DMA_DCR_SINC_MASK)
|
|
#define DMA_DCR_EADREQ_MASK (0x800000U)
|
|
#define DMA_DCR_EADREQ_SHIFT (23U)
|
|
#define DMA_DCR_EADREQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_EADREQ_SHIFT)) & DMA_DCR_EADREQ_MASK)
|
|
#define DMA_DCR_AA_MASK (0x10000000U)
|
|
#define DMA_DCR_AA_SHIFT (28U)
|
|
#define DMA_DCR_AA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_AA_SHIFT)) & DMA_DCR_AA_MASK)
|
|
#define DMA_DCR_CS_MASK (0x20000000U)
|
|
#define DMA_DCR_CS_SHIFT (29U)
|
|
#define DMA_DCR_CS(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_CS_SHIFT)) & DMA_DCR_CS_MASK)
|
|
#define DMA_DCR_ERQ_MASK (0x40000000U)
|
|
#define DMA_DCR_ERQ_SHIFT (30U)
|
|
#define DMA_DCR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_ERQ_SHIFT)) & DMA_DCR_ERQ_MASK)
|
|
#define DMA_DCR_EINT_MASK (0x80000000U)
|
|
#define DMA_DCR_EINT_SHIFT (31U)
|
|
#define DMA_DCR_EINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_EINT_SHIFT)) & DMA_DCR_EINT_MASK)
|
|
|
|
/* The count of DMA_DCR */
|
|
#define DMA_DCR_COUNT (4U)
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group DMA_Register_Masks */
|
|
|
|
/* DMA - Peripheral instance base addresses */
|
|
/** Peripheral DMA base address */
|
|
#define DMA_BASE (0x40008000u)
|
|
/** Peripheral DMA base pointer */
|
|
#define DMA0 ((DMA_Type *)DMA_BASE)
|
|
/** Array initializer of DMA peripheral base addresses */
|
|
#define DMA_BASE_ADDRS \
|
|
{ DMA_BASE }
|
|
/** Array initializer of DMA peripheral base pointers */
|
|
#define DMA_BASE_PTRS \
|
|
{ DMA0 }
|
|
/** Interrupt vectors for the DMA peripheral type */
|
|
#define DMA_CHN_IRQS \
|
|
{ \
|
|
{ DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } \
|
|
}
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group DMA_Peripheral_Access_Layer */
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- DMAMUX Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** DMAMUX - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
|
|
} DMAMUX_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- DMAMUX Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name CHCFG - Channel Configuration register */
|
|
#define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
|
|
#define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
|
|
#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
|
|
#define DMAMUX_CHCFG_TRIG_MASK (0x40U)
|
|
#define DMAMUX_CHCFG_TRIG_SHIFT (6U)
|
|
#define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
|
|
#define DMAMUX_CHCFG_ENBL_MASK (0x80U)
|
|
#define DMAMUX_CHCFG_ENBL_SHIFT (7U)
|
|
#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
|
|
|
|
/* The count of DMAMUX_CHCFG */
|
|
#define DMAMUX_CHCFG_COUNT (4U)
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group DMAMUX_Register_Masks */
|
|
|
|
/* DMAMUX - Peripheral instance base addresses */
|
|
/** Peripheral DMAMUX0 base address */
|
|
#define DMAMUX0_BASE (0x40021000u)
|
|
/** Peripheral DMAMUX0 base pointer */
|
|
#define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
|
|
/** Array initializer of DMAMUX peripheral base addresses */
|
|
#define DMAMUX_BASE_ADDRS \
|
|
{ DMAMUX0_BASE }
|
|
/** Array initializer of DMAMUX peripheral base pointers */
|
|
#define DMAMUX_BASE_PTRS \
|
|
{ DMAMUX0 }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group DMAMUX_Peripheral_Access_Layer */
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- FGPIO Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** FGPIO - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
|
|
__O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
|
|
__O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
|
|
__O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
|
|
__I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
|
|
__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
|
|
} FGPIO_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- FGPIO Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup FGPIO_Register_Masks FGPIO Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name PDOR - Port Data Output Register */
|
|
#define FGPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
|
|
#define FGPIO_PDOR_PDO_SHIFT (0U)
|
|
#define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDOR_PDO_SHIFT)) & FGPIO_PDOR_PDO_MASK)
|
|
|
|
/*! @name PSOR - Port Set Output Register */
|
|
#define FGPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
|
|
#define FGPIO_PSOR_PTSO_SHIFT (0U)
|
|
#define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PSOR_PTSO_SHIFT)) & FGPIO_PSOR_PTSO_MASK)
|
|
|
|
/*! @name PCOR - Port Clear Output Register */
|
|
#define FGPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
|
|
#define FGPIO_PCOR_PTCO_SHIFT (0U)
|
|
#define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PCOR_PTCO_SHIFT)) & FGPIO_PCOR_PTCO_MASK)
|
|
|
|
/*! @name PTOR - Port Toggle Output Register */
|
|
#define FGPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
|
|
#define FGPIO_PTOR_PTTO_SHIFT (0U)
|
|
#define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PTOR_PTTO_SHIFT)) & FGPIO_PTOR_PTTO_MASK)
|
|
|
|
/*! @name PDIR - Port Data Input Register */
|
|
#define FGPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
|
|
#define FGPIO_PDIR_PDI_SHIFT (0U)
|
|
#define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDIR_PDI_SHIFT)) & FGPIO_PDIR_PDI_MASK)
|
|
|
|
/*! @name PDDR - Port Data Direction Register */
|
|
#define FGPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
|
|
#define FGPIO_PDDR_PDD_SHIFT (0U)
|
|
#define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDDR_PDD_SHIFT)) & FGPIO_PDDR_PDD_MASK)
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group FGPIO_Register_Masks */
|
|
|
|
/* FGPIO - Peripheral instance base addresses */
|
|
/** Peripheral FGPIOA base address */
|
|
#define FGPIOA_BASE (0xF80FF000u)
|
|
/** Peripheral FGPIOA base pointer */
|
|
#define FGPIOA ((FGPIO_Type *)FGPIOA_BASE)
|
|
/** Peripheral FGPIOB base address */
|
|
#define FGPIOB_BASE (0xF80FF040u)
|
|
/** Peripheral FGPIOB base pointer */
|
|
#define FGPIOB ((FGPIO_Type *)FGPIOB_BASE)
|
|
/** Peripheral FGPIOC base address */
|
|
#define FGPIOC_BASE (0xF80FF080u)
|
|
/** Peripheral FGPIOC base pointer */
|
|
#define FGPIOC ((FGPIO_Type *)FGPIOC_BASE)
|
|
/** Peripheral FGPIOD base address */
|
|
#define FGPIOD_BASE (0xF80FF0C0u)
|
|
/** Peripheral FGPIOD base pointer */
|
|
#define FGPIOD ((FGPIO_Type *)FGPIOD_BASE)
|
|
/** Peripheral FGPIOE base address */
|
|
#define FGPIOE_BASE (0xF80FF100u)
|
|
/** Peripheral FGPIOE base pointer */
|
|
#define FGPIOE ((FGPIO_Type *)FGPIOE_BASE)
|
|
/** Array initializer of FGPIO peripheral base addresses */
|
|
#define FGPIO_BASE_ADDRS \
|
|
{ FGPIOA_BASE, FGPIOB_BASE, FGPIOC_BASE, FGPIOD_BASE, FGPIOE_BASE }
|
|
/** Array initializer of FGPIO peripheral base pointers */
|
|
#define FGPIO_BASE_PTRS \
|
|
{ FGPIOA, FGPIOB, FGPIOC, FGPIOD, FGPIOE }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group FGPIO_Peripheral_Access_Layer */
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- FTFA Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** FTFA - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
|
|
__IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
|
|
__I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
|
|
__I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
|
|
__IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
|
|
__IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
|
|
__IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
|
|
__IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
|
|
__IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
|
|
__IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
|
|
__IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
|
|
__IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
|
|
__IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
|
|
__IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
|
|
__IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
|
|
__IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
|
|
__IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
|
|
__IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
|
|
__IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
|
|
__IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
|
|
} FTFA_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- FTFA Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup FTFA_Register_Masks FTFA Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name FSTAT - Flash Status Register */
|
|
#define FTFA_FSTAT_MGSTAT0_MASK (0x1U)
|
|
#define FTFA_FSTAT_MGSTAT0_SHIFT (0U)
|
|
#define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK)
|
|
#define FTFA_FSTAT_FPVIOL_MASK (0x10U)
|
|
#define FTFA_FSTAT_FPVIOL_SHIFT (4U)
|
|
#define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK)
|
|
#define FTFA_FSTAT_ACCERR_MASK (0x20U)
|
|
#define FTFA_FSTAT_ACCERR_SHIFT (5U)
|
|
#define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK)
|
|
#define FTFA_FSTAT_RDCOLERR_MASK (0x40U)
|
|
#define FTFA_FSTAT_RDCOLERR_SHIFT (6U)
|
|
#define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK)
|
|
#define FTFA_FSTAT_CCIF_MASK (0x80U)
|
|
#define FTFA_FSTAT_CCIF_SHIFT (7U)
|
|
#define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK)
|
|
|
|
/*! @name FCNFG - Flash Configuration Register */
|
|
#define FTFA_FCNFG_ERSSUSP_MASK (0x10U)
|
|
#define FTFA_FCNFG_ERSSUSP_SHIFT (4U)
|
|
#define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK)
|
|
#define FTFA_FCNFG_ERSAREQ_MASK (0x20U)
|
|
#define FTFA_FCNFG_ERSAREQ_SHIFT (5U)
|
|
#define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK)
|
|
#define FTFA_FCNFG_RDCOLLIE_MASK (0x40U)
|
|
#define FTFA_FCNFG_RDCOLLIE_SHIFT (6U)
|
|
#define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK)
|
|
#define FTFA_FCNFG_CCIE_MASK (0x80U)
|
|
#define FTFA_FCNFG_CCIE_SHIFT (7U)
|
|
#define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK)
|
|
|
|
/*! @name FSEC - Flash Security Register */
|
|
#define FTFA_FSEC_SEC_MASK (0x3U)
|
|
#define FTFA_FSEC_SEC_SHIFT (0U)
|
|
#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK)
|
|
#define FTFA_FSEC_FSLACC_MASK (0xCU)
|
|
#define FTFA_FSEC_FSLACC_SHIFT (2U)
|
|
#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK)
|
|
#define FTFA_FSEC_MEEN_MASK (0x30U)
|
|
#define FTFA_FSEC_MEEN_SHIFT (4U)
|
|
#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK)
|
|
#define FTFA_FSEC_KEYEN_MASK (0xC0U)
|
|
#define FTFA_FSEC_KEYEN_SHIFT (6U)
|
|
#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK)
|
|
|
|
/*! @name FOPT - Flash Option Register */
|
|
#define FTFA_FOPT_OPT_MASK (0xFFU)
|
|
#define FTFA_FOPT_OPT_SHIFT (0U)
|
|
#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK)
|
|
|
|
/*! @name FCCOB3 - Flash Common Command Object Registers */
|
|
#define FTFA_FCCOB3_CCOBn_MASK (0xFFU)
|
|
#define FTFA_FCCOB3_CCOBn_SHIFT (0U)
|
|
#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK)
|
|
|
|
/*! @name FCCOB2 - Flash Common Command Object Registers */
|
|
#define FTFA_FCCOB2_CCOBn_MASK (0xFFU)
|
|
#define FTFA_FCCOB2_CCOBn_SHIFT (0U)
|
|
#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK)
|
|
|
|
/*! @name FCCOB1 - Flash Common Command Object Registers */
|
|
#define FTFA_FCCOB1_CCOBn_MASK (0xFFU)
|
|
#define FTFA_FCCOB1_CCOBn_SHIFT (0U)
|
|
#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK)
|
|
|
|
/*! @name FCCOB0 - Flash Common Command Object Registers */
|
|
#define FTFA_FCCOB0_CCOBn_MASK (0xFFU)
|
|
#define FTFA_FCCOB0_CCOBn_SHIFT (0U)
|
|
#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK)
|
|
|
|
/*! @name FCCOB7 - Flash Common Command Object Registers */
|
|
#define FTFA_FCCOB7_CCOBn_MASK (0xFFU)
|
|
#define FTFA_FCCOB7_CCOBn_SHIFT (0U)
|
|
#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK)
|
|
|
|
/*! @name FCCOB6 - Flash Common Command Object Registers */
|
|
#define FTFA_FCCOB6_CCOBn_MASK (0xFFU)
|
|
#define FTFA_FCCOB6_CCOBn_SHIFT (0U)
|
|
#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK)
|
|
|
|
/*! @name FCCOB5 - Flash Common Command Object Registers */
|
|
#define FTFA_FCCOB5_CCOBn_MASK (0xFFU)
|
|
#define FTFA_FCCOB5_CCOBn_SHIFT (0U)
|
|
#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK)
|
|
|
|
/*! @name FCCOB4 - Flash Common Command Object Registers */
|
|
#define FTFA_FCCOB4_CCOBn_MASK (0xFFU)
|
|
#define FTFA_FCCOB4_CCOBn_SHIFT (0U)
|
|
#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK)
|
|
|
|
/*! @name FCCOBB - Flash Common Command Object Registers */
|
|
#define FTFA_FCCOBB_CCOBn_MASK (0xFFU)
|
|
#define FTFA_FCCOBB_CCOBn_SHIFT (0U)
|
|
#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK)
|
|
|
|
/*! @name FCCOBA - Flash Common Command Object Registers */
|
|
#define FTFA_FCCOBA_CCOBn_MASK (0xFFU)
|
|
#define FTFA_FCCOBA_CCOBn_SHIFT (0U)
|
|
#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK)
|
|
|
|
/*! @name FCCOB9 - Flash Common Command Object Registers */
|
|
#define FTFA_FCCOB9_CCOBn_MASK (0xFFU)
|
|
#define FTFA_FCCOB9_CCOBn_SHIFT (0U)
|
|
#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK)
|
|
|
|
/*! @name FCCOB8 - Flash Common Command Object Registers */
|
|
#define FTFA_FCCOB8_CCOBn_MASK (0xFFU)
|
|
#define FTFA_FCCOB8_CCOBn_SHIFT (0U)
|
|
#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK)
|
|
|
|
/*! @name FPROT3 - Program Flash Protection Registers */
|
|
#define FTFA_FPROT3_PROT_MASK (0xFFU)
|
|
#define FTFA_FPROT3_PROT_SHIFT (0U)
|
|
#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK)
|
|
|
|
/*! @name FPROT2 - Program Flash Protection Registers */
|
|
#define FTFA_FPROT2_PROT_MASK (0xFFU)
|
|
#define FTFA_FPROT2_PROT_SHIFT (0U)
|
|
#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK)
|
|
|
|
/*! @name FPROT1 - Program Flash Protection Registers */
|
|
#define FTFA_FPROT1_PROT_MASK (0xFFU)
|
|
#define FTFA_FPROT1_PROT_SHIFT (0U)
|
|
#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK)
|
|
|
|
/*! @name FPROT0 - Program Flash Protection Registers */
|
|
#define FTFA_FPROT0_PROT_MASK (0xFFU)
|
|
#define FTFA_FPROT0_PROT_SHIFT (0U)
|
|
#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK)
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group FTFA_Register_Masks */
|
|
|
|
/* FTFA - Peripheral instance base addresses */
|
|
/** Peripheral FTFA base address */
|
|
#define FTFA_BASE (0x40020000u)
|
|
/** Peripheral FTFA base pointer */
|
|
#define FTFA ((FTFA_Type *)FTFA_BASE)
|
|
/** Array initializer of FTFA peripheral base addresses */
|
|
#define FTFA_BASE_ADDRS \
|
|
{ FTFA_BASE }
|
|
/** Array initializer of FTFA peripheral base pointers */
|
|
#define FTFA_BASE_PTRS \
|
|
{ FTFA }
|
|
/** Interrupt vectors for the FTFA peripheral type */
|
|
#define FTFA_COMMAND_COMPLETE_IRQS \
|
|
{ FTFA_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group FTFA_Peripheral_Access_Layer */
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- GPIO Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** GPIO - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
|
|
__O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
|
|
__O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
|
|
__O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
|
|
__I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
|
|
__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
|
|
} GPIO_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- GPIO Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup GPIO_Register_Masks GPIO Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name PDOR - Port Data Output Register */
|
|
#define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
|
|
#define GPIO_PDOR_PDO_SHIFT (0U)
|
|
#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
|
|
|
|
/*! @name PSOR - Port Set Output Register */
|
|
#define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
|
|
#define GPIO_PSOR_PTSO_SHIFT (0U)
|
|
#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
|
|
|
|
/*! @name PCOR - Port Clear Output Register */
|
|
#define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
|
|
#define GPIO_PCOR_PTCO_SHIFT (0U)
|
|
#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
|
|
|
|
/*! @name PTOR - Port Toggle Output Register */
|
|
#define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
|
|
#define GPIO_PTOR_PTTO_SHIFT (0U)
|
|
#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
|
|
|
|
/*! @name PDIR - Port Data Input Register */
|
|
#define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
|
|
#define GPIO_PDIR_PDI_SHIFT (0U)
|
|
#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
|
|
|
|
/*! @name PDDR - Port Data Direction Register */
|
|
#define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
|
|
#define GPIO_PDDR_PDD_SHIFT (0U)
|
|
#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group GPIO_Register_Masks */
|
|
|
|
/* GPIO - Peripheral instance base addresses */
|
|
/** Peripheral GPIOA base address */
|
|
#define GPIOA_BASE (0x400FF000u)
|
|
/** Peripheral GPIOA base pointer */
|
|
#define GPIOA ((GPIO_Type *)GPIOA_BASE)
|
|
/** Peripheral GPIOB base address */
|
|
#define GPIOB_BASE (0x400FF040u)
|
|
/** Peripheral GPIOB base pointer */
|
|
#define GPIOB ((GPIO_Type *)GPIOB_BASE)
|
|
/** Peripheral GPIOC base address */
|
|
#define GPIOC_BASE (0x400FF080u)
|
|
/** Peripheral GPIOC base pointer */
|
|
#define GPIOC ((GPIO_Type *)GPIOC_BASE)
|
|
/** Peripheral GPIOD base address */
|
|
#define GPIOD_BASE (0x400FF0C0u)
|
|
/** Peripheral GPIOD base pointer */
|
|
#define GPIOD ((GPIO_Type *)GPIOD_BASE)
|
|
/** Peripheral GPIOE base address */
|
|
#define GPIOE_BASE (0x400FF100u)
|
|
/** Peripheral GPIOE base pointer */
|
|
#define GPIOE ((GPIO_Type *)GPIOE_BASE)
|
|
/** Array initializer of GPIO peripheral base addresses */
|
|
#define GPIO_BASE_ADDRS \
|
|
{ GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
|
|
/** Array initializer of GPIO peripheral base pointers */
|
|
#define GPIO_BASE_PTRS \
|
|
{ GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group GPIO_Peripheral_Access_Layer */
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- I2C Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** I2C - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
|
|
__IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
|
|
__IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
|
|
__IO uint8_t S; /**< I2C Status register, offset: 0x3 */
|
|
__IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
|
|
__IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
|
|
__IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
|
|
__IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
|
|
__IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
|
|
__IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
|
|
__IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
|
|
__IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
|
|
} I2C_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- I2C Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup I2C_Register_Masks I2C Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name A1 - I2C Address Register 1 */
|
|
#define I2C_A1_AD_MASK (0xFEU)
|
|
#define I2C_A1_AD_SHIFT (1U)
|
|
#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
|
|
|
|
/*! @name F - I2C Frequency Divider register */
|
|
#define I2C_F_ICR_MASK (0x3FU)
|
|
#define I2C_F_ICR_SHIFT (0U)
|
|
#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
|
|
#define I2C_F_MULT_MASK (0xC0U)
|
|
#define I2C_F_MULT_SHIFT (6U)
|
|
#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
|
|
|
|
/*! @name C1 - I2C Control Register 1 */
|
|
#define I2C_C1_DMAEN_MASK (0x1U)
|
|
#define I2C_C1_DMAEN_SHIFT (0U)
|
|
#define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
|
|
#define I2C_C1_WUEN_MASK (0x2U)
|
|
#define I2C_C1_WUEN_SHIFT (1U)
|
|
#define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
|
|
#define I2C_C1_RSTA_MASK (0x4U)
|
|
#define I2C_C1_RSTA_SHIFT (2U)
|
|
#define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
|
|
#define I2C_C1_TXAK_MASK (0x8U)
|
|
#define I2C_C1_TXAK_SHIFT (3U)
|
|
#define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
|
|
#define I2C_C1_TX_MASK (0x10U)
|
|
#define I2C_C1_TX_SHIFT (4U)
|
|
#define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
|
|
#define I2C_C1_MST_MASK (0x20U)
|
|
#define I2C_C1_MST_SHIFT (5U)
|
|
#define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
|
|
#define I2C_C1_IICIE_MASK (0x40U)
|
|
#define I2C_C1_IICIE_SHIFT (6U)
|
|
#define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
|
|
#define I2C_C1_IICEN_MASK (0x80U)
|
|
#define I2C_C1_IICEN_SHIFT (7U)
|
|
#define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
|
|
|
|
/*! @name S - I2C Status register */
|
|
#define I2C_S_RXAK_MASK (0x1U)
|
|
#define I2C_S_RXAK_SHIFT (0U)
|
|
#define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
|
|
#define I2C_S_IICIF_MASK (0x2U)
|
|
#define I2C_S_IICIF_SHIFT (1U)
|
|
#define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
|
|
#define I2C_S_SRW_MASK (0x4U)
|
|
#define I2C_S_SRW_SHIFT (2U)
|
|
#define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
|
|
#define I2C_S_RAM_MASK (0x8U)
|
|
#define I2C_S_RAM_SHIFT (3U)
|
|
#define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
|
|
#define I2C_S_ARBL_MASK (0x10U)
|
|
#define I2C_S_ARBL_SHIFT (4U)
|
|
#define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
|
|
#define I2C_S_BUSY_MASK (0x20U)
|
|
#define I2C_S_BUSY_SHIFT (5U)
|
|
#define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
|
|
#define I2C_S_IAAS_MASK (0x40U)
|
|
#define I2C_S_IAAS_SHIFT (6U)
|
|
#define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
|
|
#define I2C_S_TCF_MASK (0x80U)
|
|
#define I2C_S_TCF_SHIFT (7U)
|
|
#define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
|
|
|
|
/*! @name D - I2C Data I/O register */
|
|
#define I2C_D_DATA_MASK (0xFFU)
|
|
#define I2C_D_DATA_SHIFT (0U)
|
|
#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
|
|
|
|
/*! @name C2 - I2C Control Register 2 */
|
|
#define I2C_C2_AD_MASK (0x7U)
|
|
#define I2C_C2_AD_SHIFT (0U)
|
|
#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
|
|
#define I2C_C2_RMEN_MASK (0x8U)
|
|
#define I2C_C2_RMEN_SHIFT (3U)
|
|
#define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
|
|
#define I2C_C2_SBRC_MASK (0x10U)
|
|
#define I2C_C2_SBRC_SHIFT (4U)
|
|
#define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
|
|
#define I2C_C2_HDRS_MASK (0x20U)
|
|
#define I2C_C2_HDRS_SHIFT (5U)
|
|
#define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
|
|
#define I2C_C2_ADEXT_MASK (0x40U)
|
|
#define I2C_C2_ADEXT_SHIFT (6U)
|
|
#define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
|
|
#define I2C_C2_GCAEN_MASK (0x80U)
|
|
#define I2C_C2_GCAEN_SHIFT (7U)
|
|
#define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
|
|
|
|
/*! @name FLT - I2C Programmable Input Glitch Filter register */
|
|
#define I2C_FLT_FLT_MASK (0x1FU)
|
|
#define I2C_FLT_FLT_SHIFT (0U)
|
|
#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
|
|
#define I2C_FLT_STOPIE_MASK (0x20U)
|
|
#define I2C_FLT_STOPIE_SHIFT (5U)
|
|
#define I2C_FLT_STOPIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPIE_SHIFT)) & I2C_FLT_STOPIE_MASK)
|
|
#define I2C_FLT_STOPF_MASK (0x40U)
|
|
#define I2C_FLT_STOPF_SHIFT (6U)
|
|
#define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
|
|
#define I2C_FLT_SHEN_MASK (0x80U)
|
|
#define I2C_FLT_SHEN_SHIFT (7U)
|
|
#define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
|
|
|
|
/*! @name RA - I2C Range Address register */
|
|
#define I2C_RA_RAD_MASK (0xFEU)
|
|
#define I2C_RA_RAD_SHIFT (1U)
|
|
#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
|
|
|
|
/*! @name SMB - I2C SMBus Control and Status register */
|
|
#define I2C_SMB_SHTF2IE_MASK (0x1U)
|
|
#define I2C_SMB_SHTF2IE_SHIFT (0U)
|
|
#define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
|
|
#define I2C_SMB_SHTF2_MASK (0x2U)
|
|
#define I2C_SMB_SHTF2_SHIFT (1U)
|
|
#define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
|
|
#define I2C_SMB_SHTF1_MASK (0x4U)
|
|
#define I2C_SMB_SHTF1_SHIFT (2U)
|
|
#define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
|
|
#define I2C_SMB_SLTF_MASK (0x8U)
|
|
#define I2C_SMB_SLTF_SHIFT (3U)
|
|
#define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
|
|
#define I2C_SMB_TCKSEL_MASK (0x10U)
|
|
#define I2C_SMB_TCKSEL_SHIFT (4U)
|
|
#define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
|
|
#define I2C_SMB_SIICAEN_MASK (0x20U)
|
|
#define I2C_SMB_SIICAEN_SHIFT (5U)
|
|
#define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
|
|
#define I2C_SMB_ALERTEN_MASK (0x40U)
|
|
#define I2C_SMB_ALERTEN_SHIFT (6U)
|
|
#define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
|
|
#define I2C_SMB_FACK_MASK (0x80U)
|
|
#define I2C_SMB_FACK_SHIFT (7U)
|
|
#define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
|
|
|
|
/*! @name A2 - I2C Address Register 2 */
|
|
#define I2C_A2_SAD_MASK (0xFEU)
|
|
#define I2C_A2_SAD_SHIFT (1U)
|
|
#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
|
|
|
|
/*! @name SLTH - I2C SCL Low Timeout Register High */
|
|
#define I2C_SLTH_SSLT_MASK (0xFFU)
|
|
#define I2C_SLTH_SSLT_SHIFT (0U)
|
|
#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
|
|
|
|
/*! @name SLTL - I2C SCL Low Timeout Register Low */
|
|
#define I2C_SLTL_SSLT_MASK (0xFFU)
|
|
#define I2C_SLTL_SSLT_SHIFT (0U)
|
|
#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group I2C_Register_Masks */
|
|
|
|
/* I2C - Peripheral instance base addresses */
|
|
/** Peripheral I2C0 base address */
|
|
#define I2C0_BASE (0x40066000u)
|
|
/** Peripheral I2C0 base pointer */
|
|
#define I2C0 ((I2C_Type *)I2C0_BASE)
|
|
/** Peripheral I2C1 base address */
|
|
#define I2C1_BASE (0x40067000u)
|
|
/** Peripheral I2C1 base pointer */
|
|
#define I2C1 ((I2C_Type *)I2C1_BASE)
|
|
/** Array initializer of I2C peripheral base addresses */
|
|
#define I2C_BASE_ADDRS \
|
|
{ I2C0_BASE, I2C1_BASE }
|
|
/** Array initializer of I2C peripheral base pointers */
|
|
#define I2C_BASE_PTRS \
|
|
{ I2C0, I2C1 }
|
|
/** Interrupt vectors for the I2C peripheral type */
|
|
#define I2C_IRQS \
|
|
{ I2C0_IRQn, I2C1_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group I2C_Peripheral_Access_Layer */
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- LLWU Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** LLWU - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
|
|
__IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
|
|
__IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
|
|
__IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
|
|
__IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
|
|
__IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
|
|
__IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
|
|
__I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
|
|
__IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
|
|
__IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
|
|
} LLWU_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- LLWU Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup LLWU_Register_Masks LLWU Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name PE1 - LLWU Pin Enable 1 register */
|
|
#define LLWU_PE1_WUPE0_MASK (0x3U)
|
|
#define LLWU_PE1_WUPE0_SHIFT (0U)
|
|
#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
|
|
#define LLWU_PE1_WUPE1_MASK (0xCU)
|
|
#define LLWU_PE1_WUPE1_SHIFT (2U)
|
|
#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
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#define LLWU_PE1_WUPE2_MASK (0x30U)
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#define LLWU_PE1_WUPE2_SHIFT (4U)
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#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
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#define LLWU_PE1_WUPE3_MASK (0xC0U)
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#define LLWU_PE1_WUPE3_SHIFT (6U)
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#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
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/*! @name PE2 - LLWU Pin Enable 2 register */
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#define LLWU_PE2_WUPE4_MASK (0x3U)
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#define LLWU_PE2_WUPE4_SHIFT (0U)
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#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
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#define LLWU_PE2_WUPE5_MASK (0xCU)
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#define LLWU_PE2_WUPE5_SHIFT (2U)
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#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
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#define LLWU_PE2_WUPE6_MASK (0x30U)
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#define LLWU_PE2_WUPE6_SHIFT (4U)
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#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
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#define LLWU_PE2_WUPE7_MASK (0xC0U)
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#define LLWU_PE2_WUPE7_SHIFT (6U)
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#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
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/*! @name PE3 - LLWU Pin Enable 3 register */
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#define LLWU_PE3_WUPE8_MASK (0x3U)
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#define LLWU_PE3_WUPE8_SHIFT (0U)
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#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
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#define LLWU_PE3_WUPE9_MASK (0xCU)
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#define LLWU_PE3_WUPE9_SHIFT (2U)
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#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
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#define LLWU_PE3_WUPE10_MASK (0x30U)
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#define LLWU_PE3_WUPE10_SHIFT (4U)
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#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
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#define LLWU_PE3_WUPE11_MASK (0xC0U)
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#define LLWU_PE3_WUPE11_SHIFT (6U)
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#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
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/*! @name PE4 - LLWU Pin Enable 4 register */
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#define LLWU_PE4_WUPE12_MASK (0x3U)
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#define LLWU_PE4_WUPE12_SHIFT (0U)
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#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
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#define LLWU_PE4_WUPE13_MASK (0xCU)
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#define LLWU_PE4_WUPE13_SHIFT (2U)
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#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
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#define LLWU_PE4_WUPE14_MASK (0x30U)
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#define LLWU_PE4_WUPE14_SHIFT (4U)
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#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
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#define LLWU_PE4_WUPE15_MASK (0xC0U)
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#define LLWU_PE4_WUPE15_SHIFT (6U)
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#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
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/*! @name ME - LLWU Module Enable register */
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#define LLWU_ME_WUME0_MASK (0x1U)
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#define LLWU_ME_WUME0_SHIFT (0U)
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#define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
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#define LLWU_ME_WUME1_MASK (0x2U)
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#define LLWU_ME_WUME1_SHIFT (1U)
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#define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
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#define LLWU_ME_WUME2_MASK (0x4U)
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#define LLWU_ME_WUME2_SHIFT (2U)
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#define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
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#define LLWU_ME_WUME3_MASK (0x8U)
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#define LLWU_ME_WUME3_SHIFT (3U)
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#define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
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#define LLWU_ME_WUME4_MASK (0x10U)
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#define LLWU_ME_WUME4_SHIFT (4U)
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#define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
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#define LLWU_ME_WUME5_MASK (0x20U)
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#define LLWU_ME_WUME5_SHIFT (5U)
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#define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
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#define LLWU_ME_WUME6_MASK (0x40U)
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#define LLWU_ME_WUME6_SHIFT (6U)
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#define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
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#define LLWU_ME_WUME7_MASK (0x80U)
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#define LLWU_ME_WUME7_SHIFT (7U)
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#define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
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/*! @name F1 - LLWU Flag 1 register */
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#define LLWU_F1_WUF0_MASK (0x1U)
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#define LLWU_F1_WUF0_SHIFT (0U)
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#define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK)
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#define LLWU_F1_WUF1_MASK (0x2U)
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#define LLWU_F1_WUF1_SHIFT (1U)
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#define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK)
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#define LLWU_F1_WUF2_MASK (0x4U)
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#define LLWU_F1_WUF2_SHIFT (2U)
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#define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK)
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#define LLWU_F1_WUF3_MASK (0x8U)
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#define LLWU_F1_WUF3_SHIFT (3U)
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#define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK)
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#define LLWU_F1_WUF4_MASK (0x10U)
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#define LLWU_F1_WUF4_SHIFT (4U)
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#define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK)
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#define LLWU_F1_WUF5_MASK (0x20U)
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#define LLWU_F1_WUF5_SHIFT (5U)
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#define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK)
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#define LLWU_F1_WUF6_MASK (0x40U)
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#define LLWU_F1_WUF6_SHIFT (6U)
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#define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK)
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#define LLWU_F1_WUF7_MASK (0x80U)
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#define LLWU_F1_WUF7_SHIFT (7U)
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#define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK)
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/*! @name F2 - LLWU Flag 2 register */
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#define LLWU_F2_WUF8_MASK (0x1U)
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#define LLWU_F2_WUF8_SHIFT (0U)
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#define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK)
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#define LLWU_F2_WUF9_MASK (0x2U)
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#define LLWU_F2_WUF9_SHIFT (1U)
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#define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK)
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#define LLWU_F2_WUF10_MASK (0x4U)
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#define LLWU_F2_WUF10_SHIFT (2U)
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#define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK)
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#define LLWU_F2_WUF11_MASK (0x8U)
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#define LLWU_F2_WUF11_SHIFT (3U)
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#define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK)
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#define LLWU_F2_WUF12_MASK (0x10U)
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#define LLWU_F2_WUF12_SHIFT (4U)
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#define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK)
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#define LLWU_F2_WUF13_MASK (0x20U)
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#define LLWU_F2_WUF13_SHIFT (5U)
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#define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK)
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#define LLWU_F2_WUF14_MASK (0x40U)
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#define LLWU_F2_WUF14_SHIFT (6U)
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#define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK)
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#define LLWU_F2_WUF15_MASK (0x80U)
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#define LLWU_F2_WUF15_SHIFT (7U)
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#define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK)
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/*! @name F3 - LLWU Flag 3 register */
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#define LLWU_F3_MWUF0_MASK (0x1U)
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#define LLWU_F3_MWUF0_SHIFT (0U)
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#define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK)
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#define LLWU_F3_MWUF1_MASK (0x2U)
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#define LLWU_F3_MWUF1_SHIFT (1U)
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#define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK)
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#define LLWU_F3_MWUF2_MASK (0x4U)
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#define LLWU_F3_MWUF2_SHIFT (2U)
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#define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK)
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#define LLWU_F3_MWUF3_MASK (0x8U)
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#define LLWU_F3_MWUF3_SHIFT (3U)
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#define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK)
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#define LLWU_F3_MWUF4_MASK (0x10U)
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#define LLWU_F3_MWUF4_SHIFT (4U)
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#define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK)
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#define LLWU_F3_MWUF5_MASK (0x20U)
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#define LLWU_F3_MWUF5_SHIFT (5U)
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#define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK)
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#define LLWU_F3_MWUF6_MASK (0x40U)
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|
#define LLWU_F3_MWUF6_SHIFT (6U)
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#define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK)
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#define LLWU_F3_MWUF7_MASK (0x80U)
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#define LLWU_F3_MWUF7_SHIFT (7U)
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#define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK)
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|
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/*! @name FILT1 - LLWU Pin Filter 1 register */
|
|
#define LLWU_FILT1_FILTSEL_MASK (0xFU)
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|
#define LLWU_FILT1_FILTSEL_SHIFT (0U)
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|
#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
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|
#define LLWU_FILT1_FILTE_MASK (0x60U)
|
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#define LLWU_FILT1_FILTE_SHIFT (5U)
|
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#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
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|
#define LLWU_FILT1_FILTF_MASK (0x80U)
|
|
#define LLWU_FILT1_FILTF_SHIFT (7U)
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#define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
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|
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/*! @name FILT2 - LLWU Pin Filter 2 register */
|
|
#define LLWU_FILT2_FILTSEL_MASK (0xFU)
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#define LLWU_FILT2_FILTSEL_SHIFT (0U)
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|
#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
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|
#define LLWU_FILT2_FILTE_MASK (0x60U)
|
|
#define LLWU_FILT2_FILTE_SHIFT (5U)
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#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
|
|
#define LLWU_FILT2_FILTF_MASK (0x80U)
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|
#define LLWU_FILT2_FILTF_SHIFT (7U)
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#define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
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|
|
/*!
|
|
* @}
|
|
*/ /* end of group LLWU_Register_Masks */
|
|
|
|
/* LLWU - Peripheral instance base addresses */
|
|
/** Peripheral LLWU base address */
|
|
#define LLWU_BASE (0x4007C000u)
|
|
/** Peripheral LLWU base pointer */
|
|
#define LLWU ((LLWU_Type *)LLWU_BASE)
|
|
/** Array initializer of LLWU peripheral base addresses */
|
|
#define LLWU_BASE_ADDRS \
|
|
{ LLWU_BASE }
|
|
/** Array initializer of LLWU peripheral base pointers */
|
|
#define LLWU_BASE_PTRS \
|
|
{ LLWU }
|
|
/** Interrupt vectors for the LLWU peripheral type */
|
|
#define LLWU_IRQS \
|
|
{ LLWU_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group LLWU_Peripheral_Access_Layer */
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- LPTMR Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** LPTMR - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
|
|
__IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
|
|
__IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
|
|
__IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
|
|
} LPTMR_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- LPTMR Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup LPTMR_Register_Masks LPTMR Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name CSR - Low Power Timer Control Status Register */
|
|
#define LPTMR_CSR_TEN_MASK (0x1U)
|
|
#define LPTMR_CSR_TEN_SHIFT (0U)
|
|
#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
|
|
#define LPTMR_CSR_TMS_MASK (0x2U)
|
|
#define LPTMR_CSR_TMS_SHIFT (1U)
|
|
#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
|
|
#define LPTMR_CSR_TFC_MASK (0x4U)
|
|
#define LPTMR_CSR_TFC_SHIFT (2U)
|
|
#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
|
|
#define LPTMR_CSR_TPP_MASK (0x8U)
|
|
#define LPTMR_CSR_TPP_SHIFT (3U)
|
|
#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
|
|
#define LPTMR_CSR_TPS_MASK (0x30U)
|
|
#define LPTMR_CSR_TPS_SHIFT (4U)
|
|
#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
|
|
#define LPTMR_CSR_TIE_MASK (0x40U)
|
|
#define LPTMR_CSR_TIE_SHIFT (6U)
|
|
#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
|
|
#define LPTMR_CSR_TCF_MASK (0x80U)
|
|
#define LPTMR_CSR_TCF_SHIFT (7U)
|
|
#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
|
|
|
|
/*! @name PSR - Low Power Timer Prescale Register */
|
|
#define LPTMR_PSR_PCS_MASK (0x3U)
|
|
#define LPTMR_PSR_PCS_SHIFT (0U)
|
|
#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
|
|
#define LPTMR_PSR_PBYP_MASK (0x4U)
|
|
#define LPTMR_PSR_PBYP_SHIFT (2U)
|
|
#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
|
|
#define LPTMR_PSR_PRESCALE_MASK (0x78U)
|
|
#define LPTMR_PSR_PRESCALE_SHIFT (3U)
|
|
#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
|
|
|
|
/*! @name CMR - Low Power Timer Compare Register */
|
|
#define LPTMR_CMR_COMPARE_MASK (0xFFFFU)
|
|
#define LPTMR_CMR_COMPARE_SHIFT (0U)
|
|
#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
|
|
|
|
/*! @name CNR - Low Power Timer Counter Register */
|
|
#define LPTMR_CNR_COUNTER_MASK (0xFFFFU)
|
|
#define LPTMR_CNR_COUNTER_SHIFT (0U)
|
|
#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group LPTMR_Register_Masks */
|
|
|
|
/* LPTMR - Peripheral instance base addresses */
|
|
/** Peripheral LPTMR0 base address */
|
|
#define LPTMR0_BASE (0x40040000u)
|
|
/** Peripheral LPTMR0 base pointer */
|
|
#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
|
|
/** Array initializer of LPTMR peripheral base addresses */
|
|
#define LPTMR_BASE_ADDRS \
|
|
{ LPTMR0_BASE }
|
|
/** Array initializer of LPTMR peripheral base pointers */
|
|
#define LPTMR_BASE_PTRS \
|
|
{ LPTMR0 }
|
|
/** Interrupt vectors for the LPTMR peripheral type */
|
|
#define LPTMR_IRQS \
|
|
{ LPTMR0_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group LPTMR_Peripheral_Access_Layer */
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- MCG Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** MCG - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
|
|
__IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
|
|
__IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
|
|
__IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
|
|
__IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
|
|
__IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
|
|
__IO uint8_t S; /**< MCG Status Register, offset: 0x6 */
|
|
uint8_t RESERVED_0[1];
|
|
__IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
|
|
uint8_t RESERVED_1[1];
|
|
__IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
|
|
__IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
|
|
__I uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
|
|
__IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
|
|
__I uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */
|
|
__I uint8_t C10; /**< MCG Control 10 Register, offset: 0xF */
|
|
} MCG_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- MCG Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup MCG_Register_Masks MCG Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name C1 - MCG Control 1 Register */
|
|
#define MCG_C1_IREFSTEN_MASK (0x1U)
|
|
#define MCG_C1_IREFSTEN_SHIFT (0U)
|
|
#define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
|
|
#define MCG_C1_IRCLKEN_MASK (0x2U)
|
|
#define MCG_C1_IRCLKEN_SHIFT (1U)
|
|
#define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
|
|
#define MCG_C1_IREFS_MASK (0x4U)
|
|
#define MCG_C1_IREFS_SHIFT (2U)
|
|
#define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
|
|
#define MCG_C1_FRDIV_MASK (0x38U)
|
|
#define MCG_C1_FRDIV_SHIFT (3U)
|
|
#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
|
|
#define MCG_C1_CLKS_MASK (0xC0U)
|
|
#define MCG_C1_CLKS_SHIFT (6U)
|
|
#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
|
|
|
|
/*! @name C2 - MCG Control 2 Register */
|
|
#define MCG_C2_IRCS_MASK (0x1U)
|
|
#define MCG_C2_IRCS_SHIFT (0U)
|
|
#define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
|
|
#define MCG_C2_LP_MASK (0x2U)
|
|
#define MCG_C2_LP_SHIFT (1U)
|
|
#define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
|
|
#define MCG_C2_EREFS0_MASK (0x4U)
|
|
#define MCG_C2_EREFS0_SHIFT (2U)
|
|
#define MCG_C2_EREFS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS0_SHIFT)) & MCG_C2_EREFS0_MASK)
|
|
#define MCG_C2_HGO0_MASK (0x8U)
|
|
#define MCG_C2_HGO0_SHIFT (3U)
|
|
#define MCG_C2_HGO0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO0_SHIFT)) & MCG_C2_HGO0_MASK)
|
|
#define MCG_C2_RANGE0_MASK (0x30U)
|
|
#define MCG_C2_RANGE0_SHIFT (4U)
|
|
#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE0_SHIFT)) & MCG_C2_RANGE0_MASK)
|
|
#define MCG_C2_LOCRE0_MASK (0x80U)
|
|
#define MCG_C2_LOCRE0_SHIFT (7U)
|
|
#define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
|
|
|
|
/*! @name C3 - MCG Control 3 Register */
|
|
#define MCG_C3_SCTRIM_MASK (0xFFU)
|
|
#define MCG_C3_SCTRIM_SHIFT (0U)
|
|
#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
|
|
|
|
/*! @name C4 - MCG Control 4 Register */
|
|
#define MCG_C4_SCFTRIM_MASK (0x1U)
|
|
#define MCG_C4_SCFTRIM_SHIFT (0U)
|
|
#define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
|
|
#define MCG_C4_FCTRIM_MASK (0x1EU)
|
|
#define MCG_C4_FCTRIM_SHIFT (1U)
|
|
#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
|
|
#define MCG_C4_DRST_DRS_MASK (0x60U)
|
|
#define MCG_C4_DRST_DRS_SHIFT (5U)
|
|
#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
|
|
#define MCG_C4_DMX32_MASK (0x80U)
|
|
#define MCG_C4_DMX32_SHIFT (7U)
|
|
#define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
|
|
|
|
/*! @name C5 - MCG Control 5 Register */
|
|
#define MCG_C5_PRDIV0_MASK (0x1FU)
|
|
#define MCG_C5_PRDIV0_SHIFT (0U)
|
|
#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK)
|
|
#define MCG_C5_PLLSTEN0_MASK (0x20U)
|
|
#define MCG_C5_PLLSTEN0_SHIFT (5U)
|
|
#define MCG_C5_PLLSTEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK)
|
|
#define MCG_C5_PLLCLKEN0_MASK (0x40U)
|
|
#define MCG_C5_PLLCLKEN0_SHIFT (6U)
|
|
#define MCG_C5_PLLCLKEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK)
|
|
|
|
/*! @name C6 - MCG Control 6 Register */
|
|
#define MCG_C6_VDIV0_MASK (0x1FU)
|
|
#define MCG_C6_VDIV0_SHIFT (0U)
|
|
#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK)
|
|
#define MCG_C6_CME0_MASK (0x20U)
|
|
#define MCG_C6_CME0_SHIFT (5U)
|
|
#define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
|
|
#define MCG_C6_PLLS_MASK (0x40U)
|
|
#define MCG_C6_PLLS_SHIFT (6U)
|
|
#define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)
|
|
#define MCG_C6_LOLIE0_MASK (0x80U)
|
|
#define MCG_C6_LOLIE0_SHIFT (7U)
|
|
#define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)
|
|
|
|
/*! @name S - MCG Status Register */
|
|
#define MCG_S_IRCST_MASK (0x1U)
|
|
#define MCG_S_IRCST_SHIFT (0U)
|
|
#define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
|
|
#define MCG_S_OSCINIT0_MASK (0x2U)
|
|
#define MCG_S_OSCINIT0_SHIFT (1U)
|
|
#define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
|
|
#define MCG_S_CLKST_MASK (0xCU)
|
|
#define MCG_S_CLKST_SHIFT (2U)
|
|
#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
|
|
#define MCG_S_IREFST_MASK (0x10U)
|
|
#define MCG_S_IREFST_SHIFT (4U)
|
|
#define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
|
|
#define MCG_S_PLLST_MASK (0x20U)
|
|
#define MCG_S_PLLST_SHIFT (5U)
|
|
#define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)
|
|
#define MCG_S_LOCK0_MASK (0x40U)
|
|
#define MCG_S_LOCK0_SHIFT (6U)
|
|
#define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)
|
|
#define MCG_S_LOLS0_MASK (0x80U)
|
|
#define MCG_S_LOLS0_SHIFT (7U)
|
|
#define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)
|
|
|
|
/*! @name SC - MCG Status and Control Register */
|
|
#define MCG_SC_LOCS0_MASK (0x1U)
|
|
#define MCG_SC_LOCS0_SHIFT (0U)
|
|
#define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
|
|
#define MCG_SC_FCRDIV_MASK (0xEU)
|
|
#define MCG_SC_FCRDIV_SHIFT (1U)
|
|
#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
|
|
#define MCG_SC_FLTPRSRV_MASK (0x10U)
|
|
#define MCG_SC_FLTPRSRV_SHIFT (4U)
|
|
#define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
|
|
#define MCG_SC_ATMF_MASK (0x20U)
|
|
#define MCG_SC_ATMF_SHIFT (5U)
|
|
#define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
|
|
#define MCG_SC_ATMS_MASK (0x40U)
|
|
#define MCG_SC_ATMS_SHIFT (6U)
|
|
#define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
|
|
#define MCG_SC_ATME_MASK (0x80U)
|
|
#define MCG_SC_ATME_SHIFT (7U)
|
|
#define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
|
|
|
|
/*! @name ATCVH - MCG Auto Trim Compare Value High Register */
|
|
#define MCG_ATCVH_ATCVH_MASK (0xFFU)
|
|
#define MCG_ATCVH_ATCVH_SHIFT (0U)
|
|
#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
|
|
|
|
/*! @name ATCVL - MCG Auto Trim Compare Value Low Register */
|
|
#define MCG_ATCVL_ATCVL_MASK (0xFFU)
|
|
#define MCG_ATCVL_ATCVL_SHIFT (0U)
|
|
#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
|
|
|
|
/*! @name C8 - MCG Control 8 Register */
|
|
#define MCG_C8_LOLRE_MASK (0x40U)
|
|
#define MCG_C8_LOLRE_SHIFT (6U)
|
|
#define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group MCG_Register_Masks */
|
|
|
|
/* MCG - Peripheral instance base addresses */
|
|
/** Peripheral MCG base address */
|
|
#define MCG_BASE (0x40064000u)
|
|
/** Peripheral MCG base pointer */
|
|
#define MCG ((MCG_Type *)MCG_BASE)
|
|
/** Array initializer of MCG peripheral base addresses */
|
|
#define MCG_BASE_ADDRS \
|
|
{ MCG_BASE }
|
|
/** Array initializer of MCG peripheral base pointers */
|
|
#define MCG_BASE_PTRS \
|
|
{ MCG }
|
|
/** Interrupt vectors for the MCG peripheral type */
|
|
#define MCG_IRQS \
|
|
{ MCG_IRQn }
|
|
/* MCG C2[EREFS] backward compatibility */
|
|
#define MCG_C2_EREFS_MASK (MCG_C2_EREFS0_MASK)
|
|
#define MCG_C2_EREFS_SHIFT (MCG_C2_EREFS0_SHIFT)
|
|
#define MCG_C2_EREFS_WIDTH (MCG_C2_EREFS0_WIDTH)
|
|
#define MCG_C2_EREFS(x) (MCG_C2_EREFS0(x))
|
|
|
|
/* MCG C2[HGO] backward compatibility */
|
|
#define MCG_C2_HGO_MASK (MCG_C2_HGO0_MASK)
|
|
#define MCG_C2_HGO_SHIFT (MCG_C2_HGO0_SHIFT)
|
|
#define MCG_C2_HGO_WIDTH (MCG_C2_HGO0_WIDTH)
|
|
#define MCG_C2_HGO(x) (MCG_C2_HGO0(x))
|
|
|
|
/* MCG C2[RANGE] backward compatibility */
|
|
#define MCG_C2_RANGE_MASK (MCG_C2_RANGE0_MASK)
|
|
#define MCG_C2_RANGE_SHIFT (MCG_C2_RANGE0_SHIFT)
|
|
#define MCG_C2_RANGE_WIDTH (MCG_C2_RANGE0_WIDTH)
|
|
#define MCG_C2_RANGE(x) (MCG_C2_RANGE0(x))
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group MCG_Peripheral_Access_Layer */
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- MCM Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** MCM - Register Layout Typedef */
|
|
typedef struct {
|
|
uint8_t RESERVED_0[8];
|
|
__I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
|
|
__I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
|
|
__IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
|
|
uint8_t RESERVED_1[48];
|
|
__IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
|
|
} MCM_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- MCM Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup MCM_Register_Masks MCM Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
|
|
#define MCM_PLASC_ASC_MASK (0xFFU)
|
|
#define MCM_PLASC_ASC_SHIFT (0U)
|
|
#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
|
|
|
|
/*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
|
|
#define MCM_PLAMC_AMC_MASK (0xFFU)
|
|
#define MCM_PLAMC_AMC_SHIFT (0U)
|
|
#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
|
|
|
|
/*! @name PLACR - Platform Control Register */
|
|
#define MCM_PLACR_ARB_MASK (0x200U)
|
|
#define MCM_PLACR_ARB_SHIFT (9U)
|
|
#define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK)
|
|
#define MCM_PLACR_CFCC_MASK (0x400U)
|
|
#define MCM_PLACR_CFCC_SHIFT (10U)
|
|
#define MCM_PLACR_CFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_CFCC_SHIFT)) & MCM_PLACR_CFCC_MASK)
|
|
#define MCM_PLACR_DFCDA_MASK (0x800U)
|
|
#define MCM_PLACR_DFCDA_SHIFT (11U)
|
|
#define MCM_PLACR_DFCDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCDA_SHIFT)) & MCM_PLACR_DFCDA_MASK)
|
|
#define MCM_PLACR_DFCIC_MASK (0x1000U)
|
|
#define MCM_PLACR_DFCIC_SHIFT (12U)
|
|
#define MCM_PLACR_DFCIC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCIC_SHIFT)) & MCM_PLACR_DFCIC_MASK)
|
|
#define MCM_PLACR_DFCC_MASK (0x2000U)
|
|
#define MCM_PLACR_DFCC_SHIFT (13U)
|
|
#define MCM_PLACR_DFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCC_SHIFT)) & MCM_PLACR_DFCC_MASK)
|
|
#define MCM_PLACR_EFDS_MASK (0x4000U)
|
|
#define MCM_PLACR_EFDS_SHIFT (14U)
|
|
#define MCM_PLACR_EFDS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_EFDS_SHIFT)) & MCM_PLACR_EFDS_MASK)
|
|
#define MCM_PLACR_DFCS_MASK (0x8000U)
|
|
#define MCM_PLACR_DFCS_SHIFT (15U)
|
|
#define MCM_PLACR_DFCS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCS_SHIFT)) & MCM_PLACR_DFCS_MASK)
|
|
#define MCM_PLACR_ESFC_MASK (0x10000U)
|
|
#define MCM_PLACR_ESFC_SHIFT (16U)
|
|
#define MCM_PLACR_ESFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ESFC_SHIFT)) & MCM_PLACR_ESFC_MASK)
|
|
|
|
/*! @name CPO - Compute Operation Control Register */
|
|
#define MCM_CPO_CPOREQ_MASK (0x1U)
|
|
#define MCM_CPO_CPOREQ_SHIFT (0U)
|
|
#define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
|
|
#define MCM_CPO_CPOACK_MASK (0x2U)
|
|
#define MCM_CPO_CPOACK_SHIFT (1U)
|
|
#define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
|
|
#define MCM_CPO_CPOWOI_MASK (0x4U)
|
|
#define MCM_CPO_CPOWOI_SHIFT (2U)
|
|
#define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group MCM_Register_Masks */
|
|
|
|
/* MCM - Peripheral instance base addresses */
|
|
/** Peripheral MCM base address */
|
|
#define MCM_BASE (0xF0003000u)
|
|
/** Peripheral MCM base pointer */
|
|
#define MCM ((MCM_Type *)MCM_BASE)
|
|
/** Array initializer of MCM peripheral base addresses */
|
|
#define MCM_BASE_ADDRS \
|
|
{ MCM_BASE }
|
|
/** Array initializer of MCM peripheral base pointers */
|
|
#define MCM_BASE_PTRS \
|
|
{ MCM }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group MCM_Peripheral_Access_Layer */
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- MTB Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** MTB - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
|
|
__IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
|
|
__IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
|
|
__I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
|
|
uint8_t RESERVED_0[3824];
|
|
__I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
|
|
uint8_t RESERVED_1[156];
|
|
__I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
|
|
__I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
|
|
uint8_t RESERVED_2[8];
|
|
__I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
|
|
__I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
|
|
__I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
|
|
__I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
|
|
uint8_t RESERVED_3[8];
|
|
__I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
|
|
__I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
|
|
__I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
|
|
__I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
|
|
__I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
|
|
__I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
|
|
__I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
|
|
__I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
|
|
__I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
|
|
__I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
|
|
__I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
|
|
} MTB_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- MTB Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup MTB_Register_Masks MTB Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name POSITION - MTB Position Register */
|
|
#define MTB_POSITION_WRAP_MASK (0x4U)
|
|
#define MTB_POSITION_WRAP_SHIFT (2U)
|
|
#define MTB_POSITION_WRAP(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_WRAP_SHIFT)) & MTB_POSITION_WRAP_MASK)
|
|
#define MTB_POSITION_POINTER_MASK (0xFFFFFFF8U)
|
|
#define MTB_POSITION_POINTER_SHIFT (3U)
|
|
#define MTB_POSITION_POINTER(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << MTB_POSITION_POINTER_SHIFT)) & MTB_POSITION_POINTER_MASK)
|
|
|
|
/*! @name MASTER - MTB Master Register */
|
|
#define MTB_MASTER_MASK_MASK (0x1FU)
|
|
#define MTB_MASTER_MASK_SHIFT (0U)
|
|
#define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_MASK_SHIFT)) & MTB_MASTER_MASK_MASK)
|
|
#define MTB_MASTER_TSTARTEN_MASK (0x20U)
|
|
#define MTB_MASTER_TSTARTEN_SHIFT (5U)
|
|
#define MTB_MASTER_TSTARTEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTARTEN_SHIFT)) & MTB_MASTER_TSTARTEN_MASK)
|
|
#define MTB_MASTER_TSTOPEN_MASK (0x40U)
|
|
#define MTB_MASTER_TSTOPEN_SHIFT (6U)
|
|
#define MTB_MASTER_TSTOPEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTOPEN_SHIFT)) & MTB_MASTER_TSTOPEN_MASK)
|
|
#define MTB_MASTER_SFRWPRIV_MASK (0x80U)
|
|
#define MTB_MASTER_SFRWPRIV_SHIFT (7U)
|
|
#define MTB_MASTER_SFRWPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_SFRWPRIV_SHIFT)) & MTB_MASTER_SFRWPRIV_MASK)
|
|
#define MTB_MASTER_RAMPRIV_MASK (0x100U)
|
|
#define MTB_MASTER_RAMPRIV_SHIFT (8U)
|
|
#define MTB_MASTER_RAMPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_RAMPRIV_SHIFT)) & MTB_MASTER_RAMPRIV_MASK)
|
|
#define MTB_MASTER_HALTREQ_MASK (0x200U)
|
|
#define MTB_MASTER_HALTREQ_SHIFT (9U)
|
|
#define MTB_MASTER_HALTREQ(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_HALTREQ_SHIFT)) & MTB_MASTER_HALTREQ_MASK)
|
|
#define MTB_MASTER_EN_MASK (0x80000000U)
|
|
#define MTB_MASTER_EN_SHIFT (31U)
|
|
#define MTB_MASTER_EN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_EN_SHIFT)) & MTB_MASTER_EN_MASK)
|
|
|
|
/*! @name FLOW - MTB Flow Register */
|
|
#define MTB_FLOW_AUTOSTOP_MASK (0x1U)
|
|
#define MTB_FLOW_AUTOSTOP_SHIFT (0U)
|
|
#define MTB_FLOW_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOSTOP_SHIFT)) & MTB_FLOW_AUTOSTOP_MASK)
|
|
#define MTB_FLOW_AUTOHALT_MASK (0x2U)
|
|
#define MTB_FLOW_AUTOHALT_SHIFT (1U)
|
|
#define MTB_FLOW_AUTOHALT(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOHALT_SHIFT)) & MTB_FLOW_AUTOHALT_MASK)
|
|
#define MTB_FLOW_WATERMARK_MASK (0xFFFFFFF8U)
|
|
#define MTB_FLOW_WATERMARK_SHIFT (3U)
|
|
#define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_WATERMARK_SHIFT)) & MTB_FLOW_WATERMARK_MASK)
|
|
|
|
/*! @name BASE - MTB Base Register */
|
|
#define MTB_BASE_BASEADDR_MASK (0xFFFFFFFFU)
|
|
#define MTB_BASE_BASEADDR_SHIFT (0U)
|
|
#define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x)) << MTB_BASE_BASEADDR_SHIFT)) & MTB_BASE_BASEADDR_MASK)
|
|
|
|
/*! @name MODECTRL - Integration Mode Control Register */
|
|
#define MTB_MODECTRL_MODECTRL_MASK (0xFFFFFFFFU)
|
|
#define MTB_MODECTRL_MODECTRL_SHIFT (0U)
|
|
#define MTB_MODECTRL_MODECTRL(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << MTB_MODECTRL_MODECTRL_SHIFT)) & MTB_MODECTRL_MODECTRL_MASK)
|
|
|
|
/*! @name TAGSET - Claim TAG Set Register */
|
|
#define MTB_TAGSET_TAGSET_MASK (0xFFFFFFFFU)
|
|
#define MTB_TAGSET_TAGSET_SHIFT (0U)
|
|
#define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGSET_TAGSET_SHIFT)) & MTB_TAGSET_TAGSET_MASK)
|
|
|
|
/*! @name TAGCLEAR - Claim TAG Clear Register */
|
|
#define MTB_TAGCLEAR_TAGCLEAR_MASK (0xFFFFFFFFU)
|
|
#define MTB_TAGCLEAR_TAGCLEAR_SHIFT (0U)
|
|
#define MTB_TAGCLEAR_TAGCLEAR(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << MTB_TAGCLEAR_TAGCLEAR_SHIFT)) & MTB_TAGCLEAR_TAGCLEAR_MASK)
|
|
|
|
/*! @name LOCKACCESS - Lock Access Register */
|
|
#define MTB_LOCKACCESS_LOCKACCESS_MASK (0xFFFFFFFFU)
|
|
#define MTB_LOCKACCESS_LOCKACCESS_SHIFT (0U)
|
|
#define MTB_LOCKACCESS_LOCKACCESS(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << MTB_LOCKACCESS_LOCKACCESS_SHIFT)) & MTB_LOCKACCESS_LOCKACCESS_MASK)
|
|
|
|
/*! @name LOCKSTAT - Lock Status Register */
|
|
#define MTB_LOCKSTAT_LOCKSTAT_MASK (0xFFFFFFFFU)
|
|
#define MTB_LOCKSTAT_LOCKSTAT_SHIFT (0U)
|
|
#define MTB_LOCKSTAT_LOCKSTAT(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << MTB_LOCKSTAT_LOCKSTAT_SHIFT)) & MTB_LOCKSTAT_LOCKSTAT_MASK)
|
|
|
|
/*! @name AUTHSTAT - Authentication Status Register */
|
|
#define MTB_AUTHSTAT_BIT0_MASK (0x1U)
|
|
#define MTB_AUTHSTAT_BIT0_SHIFT (0U)
|
|
#define MTB_AUTHSTAT_BIT0(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT0_SHIFT)) & MTB_AUTHSTAT_BIT0_MASK)
|
|
#define MTB_AUTHSTAT_BIT1_MASK (0x2U)
|
|
#define MTB_AUTHSTAT_BIT1_SHIFT (1U)
|
|
#define MTB_AUTHSTAT_BIT1(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT1_SHIFT)) & MTB_AUTHSTAT_BIT1_MASK)
|
|
#define MTB_AUTHSTAT_BIT2_MASK (0x4U)
|
|
#define MTB_AUTHSTAT_BIT2_SHIFT (2U)
|
|
#define MTB_AUTHSTAT_BIT2(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT2_SHIFT)) & MTB_AUTHSTAT_BIT2_MASK)
|
|
#define MTB_AUTHSTAT_BIT3_MASK (0x8U)
|
|
#define MTB_AUTHSTAT_BIT3_SHIFT (3U)
|
|
#define MTB_AUTHSTAT_BIT3(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT3_SHIFT)) & MTB_AUTHSTAT_BIT3_MASK)
|
|
|
|
/*! @name DEVICEARCH - Device Architecture Register */
|
|
#define MTB_DEVICEARCH_DEVICEARCH_MASK (0xFFFFFFFFU)
|
|
#define MTB_DEVICEARCH_DEVICEARCH_SHIFT (0U)
|
|
#define MTB_DEVICEARCH_DEVICEARCH(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << MTB_DEVICEARCH_DEVICEARCH_SHIFT)) & MTB_DEVICEARCH_DEVICEARCH_MASK)
|
|
|
|
/*! @name DEVICECFG - Device Configuration Register */
|
|
#define MTB_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU)
|
|
#define MTB_DEVICECFG_DEVICECFG_SHIFT (0U)
|
|
#define MTB_DEVICECFG_DEVICECFG(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << MTB_DEVICECFG_DEVICECFG_SHIFT)) & MTB_DEVICECFG_DEVICECFG_MASK)
|
|
|
|
/*! @name DEVICETYPID - Device Type Identifier Register */
|
|
#define MTB_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU)
|
|
#define MTB_DEVICETYPID_DEVICETYPID_SHIFT (0U)
|
|
#define MTB_DEVICETYPID_DEVICETYPID(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << MTB_DEVICETYPID_DEVICETYPID_SHIFT)) & MTB_DEVICETYPID_DEVICETYPID_MASK)
|
|
|
|
/*! @name PERIPHID4 - Peripheral ID Register */
|
|
#define MTB_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU)
|
|
#define MTB_PERIPHID4_PERIPHID_SHIFT (0U)
|
|
#define MTB_PERIPHID4_PERIPHID(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID4_PERIPHID_SHIFT)) & MTB_PERIPHID4_PERIPHID_MASK)
|
|
|
|
/*! @name PERIPHID5 - Peripheral ID Register */
|
|
#define MTB_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU)
|
|
#define MTB_PERIPHID5_PERIPHID_SHIFT (0U)
|
|
#define MTB_PERIPHID5_PERIPHID(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID5_PERIPHID_SHIFT)) & MTB_PERIPHID5_PERIPHID_MASK)
|
|
|
|
/*! @name PERIPHID6 - Peripheral ID Register */
|
|
#define MTB_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU)
|
|
#define MTB_PERIPHID6_PERIPHID_SHIFT (0U)
|
|
#define MTB_PERIPHID6_PERIPHID(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID6_PERIPHID_SHIFT)) & MTB_PERIPHID6_PERIPHID_MASK)
|
|
|
|
/*! @name PERIPHID7 - Peripheral ID Register */
|
|
#define MTB_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU)
|
|
#define MTB_PERIPHID7_PERIPHID_SHIFT (0U)
|
|
#define MTB_PERIPHID7_PERIPHID(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID7_PERIPHID_SHIFT)) & MTB_PERIPHID7_PERIPHID_MASK)
|
|
|
|
/*! @name PERIPHID0 - Peripheral ID Register */
|
|
#define MTB_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU)
|
|
#define MTB_PERIPHID0_PERIPHID_SHIFT (0U)
|
|
#define MTB_PERIPHID0_PERIPHID(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID0_PERIPHID_SHIFT)) & MTB_PERIPHID0_PERIPHID_MASK)
|
|
|
|
/*! @name PERIPHID1 - Peripheral ID Register */
|
|
#define MTB_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU)
|
|
#define MTB_PERIPHID1_PERIPHID_SHIFT (0U)
|
|
#define MTB_PERIPHID1_PERIPHID(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID1_PERIPHID_SHIFT)) & MTB_PERIPHID1_PERIPHID_MASK)
|
|
|
|
/*! @name PERIPHID2 - Peripheral ID Register */
|
|
#define MTB_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU)
|
|
#define MTB_PERIPHID2_PERIPHID_SHIFT (0U)
|
|
#define MTB_PERIPHID2_PERIPHID(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID2_PERIPHID_SHIFT)) & MTB_PERIPHID2_PERIPHID_MASK)
|
|
|
|
/*! @name PERIPHID3 - Peripheral ID Register */
|
|
#define MTB_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU)
|
|
#define MTB_PERIPHID3_PERIPHID_SHIFT (0U)
|
|
#define MTB_PERIPHID3_PERIPHID(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID3_PERIPHID_SHIFT)) & MTB_PERIPHID3_PERIPHID_MASK)
|
|
|
|
/*! @name COMPID - Component ID Register */
|
|
#define MTB_COMPID_COMPID_MASK (0xFFFFFFFFU)
|
|
#define MTB_COMPID_COMPID_SHIFT (0U)
|
|
#define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_COMPID_COMPID_SHIFT)) & MTB_COMPID_COMPID_MASK)
|
|
|
|
/* The count of MTB_COMPID */
|
|
#define MTB_COMPID_COUNT (4U)
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group MTB_Register_Masks */
|
|
|
|
/* MTB - Peripheral instance base addresses */
|
|
/** Peripheral MTB base address */
|
|
#define MTB_BASE (0xF0000000u)
|
|
/** Peripheral MTB base pointer */
|
|
#define MTB ((MTB_Type *)MTB_BASE)
|
|
/** Array initializer of MTB peripheral base addresses */
|
|
#define MTB_BASE_ADDRS \
|
|
{ MTB_BASE }
|
|
/** Array initializer of MTB peripheral base pointers */
|
|
#define MTB_BASE_PTRS \
|
|
{ MTB }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group MTB_Peripheral_Access_Layer */
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- MTBDWT Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** MTBDWT - Register Layout Typedef */
|
|
typedef struct {
|
|
__I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
|
|
uint8_t RESERVED_0[28];
|
|
struct { /* offset: 0x20, array step: 0x10 */
|
|
__IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
|
|
__IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
|
|
__IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array
|
|
offset: 0x28, array step: 0x10 */
|
|
uint8_t RESERVED_0[4];
|
|
} COMPARATOR[2];
|
|
uint8_t RESERVED_1[448];
|
|
__IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
|
|
uint8_t RESERVED_2[3524];
|
|
__I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
|
|
__I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
|
|
__I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
|
|
__I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
|
|
__I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
|
|
__I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
|
|
__I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
|
|
__I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
|
|
__I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
|
|
__I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
|
|
__I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
|
|
} MTBDWT_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- MTBDWT Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name CTRL - MTB DWT Control Register */
|
|
#define MTBDWT_CTRL_DWTCFGCTRL_MASK (0xFFFFFFFU)
|
|
#define MTBDWT_CTRL_DWTCFGCTRL_SHIFT (0U)
|
|
#define MTBDWT_CTRL_DWTCFGCTRL(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_DWTCFGCTRL_SHIFT)) & MTBDWT_CTRL_DWTCFGCTRL_MASK)
|
|
#define MTBDWT_CTRL_NUMCMP_MASK (0xF0000000U)
|
|
#define MTBDWT_CTRL_NUMCMP_SHIFT (28U)
|
|
#define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_NUMCMP_SHIFT)) & MTBDWT_CTRL_NUMCMP_MASK)
|
|
|
|
/*! @name COMP - MTB_DWT Comparator Register */
|
|
#define MTBDWT_COMP_COMP_MASK (0xFFFFFFFFU)
|
|
#define MTBDWT_COMP_COMP_SHIFT (0U)
|
|
#define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMP_COMP_SHIFT)) & MTBDWT_COMP_COMP_MASK)
|
|
|
|
/* The count of MTBDWT_COMP */
|
|
#define MTBDWT_COMP_COUNT (2U)
|
|
|
|
/*! @name MASK - MTB_DWT Comparator Mask Register */
|
|
#define MTBDWT_MASK_MASK_MASK (0x1FU)
|
|
#define MTBDWT_MASK_MASK_SHIFT (0U)
|
|
#define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_MASK_MASK_SHIFT)) & MTBDWT_MASK_MASK_MASK)
|
|
|
|
/* The count of MTBDWT_MASK */
|
|
#define MTBDWT_MASK_COUNT (2U)
|
|
|
|
/*! @name FCT - MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1 */
|
|
#define MTBDWT_FCT_FUNCTION_MASK (0xFU)
|
|
#define MTBDWT_FCT_FUNCTION_SHIFT (0U)
|
|
#define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_FUNCTION_SHIFT)) & MTBDWT_FCT_FUNCTION_MASK)
|
|
#define MTBDWT_FCT_DATAVMATCH_MASK (0x100U)
|
|
#define MTBDWT_FCT_DATAVMATCH_SHIFT (8U)
|
|
#define MTBDWT_FCT_DATAVMATCH(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVMATCH_SHIFT)) & MTBDWT_FCT_DATAVMATCH_MASK)
|
|
#define MTBDWT_FCT_DATAVSIZE_MASK (0xC00U)
|
|
#define MTBDWT_FCT_DATAVSIZE_SHIFT (10U)
|
|
#define MTBDWT_FCT_DATAVSIZE(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVSIZE_SHIFT)) & MTBDWT_FCT_DATAVSIZE_MASK)
|
|
#define MTBDWT_FCT_DATAVADDR0_MASK (0xF000U)
|
|
#define MTBDWT_FCT_DATAVADDR0_SHIFT (12U)
|
|
#define MTBDWT_FCT_DATAVADDR0(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVADDR0_SHIFT)) & MTBDWT_FCT_DATAVADDR0_MASK)
|
|
#define MTBDWT_FCT_MATCHED_MASK (0x1000000U)
|
|
#define MTBDWT_FCT_MATCHED_SHIFT (24U)
|
|
#define MTBDWT_FCT_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_MATCHED_SHIFT)) & MTBDWT_FCT_MATCHED_MASK)
|
|
|
|
/* The count of MTBDWT_FCT */
|
|
#define MTBDWT_FCT_COUNT (2U)
|
|
|
|
/*! @name TBCTRL - MTB_DWT Trace Buffer Control Register */
|
|
#define MTBDWT_TBCTRL_ACOMP0_MASK (0x1U)
|
|
#define MTBDWT_TBCTRL_ACOMP0_SHIFT (0U)
|
|
#define MTBDWT_TBCTRL_ACOMP0(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP0_SHIFT)) & MTBDWT_TBCTRL_ACOMP0_MASK)
|
|
#define MTBDWT_TBCTRL_ACOMP1_MASK (0x2U)
|
|
#define MTBDWT_TBCTRL_ACOMP1_SHIFT (1U)
|
|
#define MTBDWT_TBCTRL_ACOMP1(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP1_SHIFT)) & MTBDWT_TBCTRL_ACOMP1_MASK)
|
|
#define MTBDWT_TBCTRL_NUMCOMP_MASK (0xF0000000U)
|
|
#define MTBDWT_TBCTRL_NUMCOMP_SHIFT (28U)
|
|
#define MTBDWT_TBCTRL_NUMCOMP(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_NUMCOMP_SHIFT)) & MTBDWT_TBCTRL_NUMCOMP_MASK)
|
|
|
|
/*! @name DEVICECFG - Device Configuration Register */
|
|
#define MTBDWT_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU)
|
|
#define MTBDWT_DEVICECFG_DEVICECFG_SHIFT (0U)
|
|
#define MTBDWT_DEVICECFG_DEVICECFG(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICECFG_DEVICECFG_SHIFT)) & MTBDWT_DEVICECFG_DEVICECFG_MASK)
|
|
|
|
/*! @name DEVICETYPID - Device Type Identifier Register */
|
|
#define MTBDWT_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU)
|
|
#define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT (0U)
|
|
#define MTBDWT_DEVICETYPID_DEVICETYPID(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT)) & MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
|
|
|
|
/*! @name PERIPHID4 - Peripheral ID Register */
|
|
#define MTBDWT_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU)
|
|
#define MTBDWT_PERIPHID4_PERIPHID_SHIFT (0U)
|
|
#define MTBDWT_PERIPHID4_PERIPHID(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID4_PERIPHID_SHIFT)) & MTBDWT_PERIPHID4_PERIPHID_MASK)
|
|
|
|
/*! @name PERIPHID5 - Peripheral ID Register */
|
|
#define MTBDWT_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU)
|
|
#define MTBDWT_PERIPHID5_PERIPHID_SHIFT (0U)
|
|
#define MTBDWT_PERIPHID5_PERIPHID(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID5_PERIPHID_SHIFT)) & MTBDWT_PERIPHID5_PERIPHID_MASK)
|
|
|
|
/*! @name PERIPHID6 - Peripheral ID Register */
|
|
#define MTBDWT_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU)
|
|
#define MTBDWT_PERIPHID6_PERIPHID_SHIFT (0U)
|
|
#define MTBDWT_PERIPHID6_PERIPHID(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID6_PERIPHID_SHIFT)) & MTBDWT_PERIPHID6_PERIPHID_MASK)
|
|
|
|
/*! @name PERIPHID7 - Peripheral ID Register */
|
|
#define MTBDWT_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU)
|
|
#define MTBDWT_PERIPHID7_PERIPHID_SHIFT (0U)
|
|
#define MTBDWT_PERIPHID7_PERIPHID(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID7_PERIPHID_SHIFT)) & MTBDWT_PERIPHID7_PERIPHID_MASK)
|
|
|
|
/*! @name PERIPHID0 - Peripheral ID Register */
|
|
#define MTBDWT_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU)
|
|
#define MTBDWT_PERIPHID0_PERIPHID_SHIFT (0U)
|
|
#define MTBDWT_PERIPHID0_PERIPHID(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID0_PERIPHID_SHIFT)) & MTBDWT_PERIPHID0_PERIPHID_MASK)
|
|
|
|
/*! @name PERIPHID1 - Peripheral ID Register */
|
|
#define MTBDWT_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU)
|
|
#define MTBDWT_PERIPHID1_PERIPHID_SHIFT (0U)
|
|
#define MTBDWT_PERIPHID1_PERIPHID(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID1_PERIPHID_SHIFT)) & MTBDWT_PERIPHID1_PERIPHID_MASK)
|
|
|
|
/*! @name PERIPHID2 - Peripheral ID Register */
|
|
#define MTBDWT_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU)
|
|
#define MTBDWT_PERIPHID2_PERIPHID_SHIFT (0U)
|
|
#define MTBDWT_PERIPHID2_PERIPHID(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID2_PERIPHID_SHIFT)) & MTBDWT_PERIPHID2_PERIPHID_MASK)
|
|
|
|
/*! @name PERIPHID3 - Peripheral ID Register */
|
|
#define MTBDWT_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU)
|
|
#define MTBDWT_PERIPHID3_PERIPHID_SHIFT (0U)
|
|
#define MTBDWT_PERIPHID3_PERIPHID(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID3_PERIPHID_SHIFT)) & MTBDWT_PERIPHID3_PERIPHID_MASK)
|
|
|
|
/*! @name COMPID - Component ID Register */
|
|
#define MTBDWT_COMPID_COMPID_MASK (0xFFFFFFFFU)
|
|
#define MTBDWT_COMPID_COMPID_SHIFT (0U)
|
|
#define MTBDWT_COMPID_COMPID(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << MTBDWT_COMPID_COMPID_SHIFT)) & MTBDWT_COMPID_COMPID_MASK)
|
|
|
|
/* The count of MTBDWT_COMPID */
|
|
#define MTBDWT_COMPID_COUNT (4U)
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group MTBDWT_Register_Masks */
|
|
|
|
/* MTBDWT - Peripheral instance base addresses */
|
|
/** Peripheral MTBDWT base address */
|
|
#define MTBDWT_BASE (0xF0001000u)
|
|
/** Peripheral MTBDWT base pointer */
|
|
#define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
|
|
/** Array initializer of MTBDWT peripheral base addresses */
|
|
#define MTBDWT_BASE_ADDRS \
|
|
{ MTBDWT_BASE }
|
|
/** Array initializer of MTBDWT peripheral base pointers */
|
|
#define MTBDWT_BASE_PTRS \
|
|
{ MTBDWT }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group MTBDWT_Peripheral_Access_Layer */
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- NV Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** NV - Register Layout Typedef */
|
|
typedef struct {
|
|
__I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
|
|
__I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
|
|
__I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
|
|
__I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
|
|
__I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
|
|
__I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
|
|
__I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
|
|
__I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
|
|
__I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
|
|
__I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
|
|
__I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
|
|
__I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
|
|
__I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
|
|
__I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
|
|
} NV_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- NV Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup NV_Register_Masks NV Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name BACKKEY3 - Backdoor Comparison Key 3. */
|
|
#define NV_BACKKEY3_KEY_MASK (0xFFU)
|
|
#define NV_BACKKEY3_KEY_SHIFT (0U)
|
|
#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
|
|
|
|
/*! @name BACKKEY2 - Backdoor Comparison Key 2. */
|
|
#define NV_BACKKEY2_KEY_MASK (0xFFU)
|
|
#define NV_BACKKEY2_KEY_SHIFT (0U)
|
|
#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
|
|
|
|
/*! @name BACKKEY1 - Backdoor Comparison Key 1. */
|
|
#define NV_BACKKEY1_KEY_MASK (0xFFU)
|
|
#define NV_BACKKEY1_KEY_SHIFT (0U)
|
|
#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
|
|
|
|
/*! @name BACKKEY0 - Backdoor Comparison Key 0. */
|
|
#define NV_BACKKEY0_KEY_MASK (0xFFU)
|
|
#define NV_BACKKEY0_KEY_SHIFT (0U)
|
|
#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
|
|
|
|
/*! @name BACKKEY7 - Backdoor Comparison Key 7. */
|
|
#define NV_BACKKEY7_KEY_MASK (0xFFU)
|
|
#define NV_BACKKEY7_KEY_SHIFT (0U)
|
|
#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
|
|
|
|
/*! @name BACKKEY6 - Backdoor Comparison Key 6. */
|
|
#define NV_BACKKEY6_KEY_MASK (0xFFU)
|
|
#define NV_BACKKEY6_KEY_SHIFT (0U)
|
|
#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
|
|
|
|
/*! @name BACKKEY5 - Backdoor Comparison Key 5. */
|
|
#define NV_BACKKEY5_KEY_MASK (0xFFU)
|
|
#define NV_BACKKEY5_KEY_SHIFT (0U)
|
|
#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
|
|
|
|
/*! @name BACKKEY4 - Backdoor Comparison Key 4. */
|
|
#define NV_BACKKEY4_KEY_MASK (0xFFU)
|
|
#define NV_BACKKEY4_KEY_SHIFT (0U)
|
|
#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
|
|
|
|
/*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */
|
|
#define NV_FPROT3_PROT_MASK (0xFFU)
|
|
#define NV_FPROT3_PROT_SHIFT (0U)
|
|
#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
|
|
|
|
/*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */
|
|
#define NV_FPROT2_PROT_MASK (0xFFU)
|
|
#define NV_FPROT2_PROT_SHIFT (0U)
|
|
#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
|
|
|
|
/*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */
|
|
#define NV_FPROT1_PROT_MASK (0xFFU)
|
|
#define NV_FPROT1_PROT_SHIFT (0U)
|
|
#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
|
|
|
|
/*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */
|
|
#define NV_FPROT0_PROT_MASK (0xFFU)
|
|
#define NV_FPROT0_PROT_SHIFT (0U)
|
|
#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
|
|
|
|
/*! @name FSEC - Non-volatile Flash Security Register */
|
|
#define NV_FSEC_SEC_MASK (0x3U)
|
|
#define NV_FSEC_SEC_SHIFT (0U)
|
|
#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
|
|
#define NV_FSEC_FSLACC_MASK (0xCU)
|
|
#define NV_FSEC_FSLACC_SHIFT (2U)
|
|
#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
|
|
#define NV_FSEC_MEEN_MASK (0x30U)
|
|
#define NV_FSEC_MEEN_SHIFT (4U)
|
|
#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
|
|
#define NV_FSEC_KEYEN_MASK (0xC0U)
|
|
#define NV_FSEC_KEYEN_SHIFT (6U)
|
|
#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
|
|
|
|
/*! @name FOPT - Non-volatile Flash Option Register */
|
|
#define NV_FOPT_LPBOOT0_MASK (0x1U)
|
|
#define NV_FOPT_LPBOOT0_SHIFT (0U)
|
|
#define NV_FOPT_LPBOOT0(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT0_SHIFT)) & NV_FOPT_LPBOOT0_MASK)
|
|
#define NV_FOPT_NMI_DIS_MASK (0x4U)
|
|
#define NV_FOPT_NMI_DIS_SHIFT (2U)
|
|
#define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
|
|
#define NV_FOPT_RESET_PIN_CFG_MASK (0x8U)
|
|
#define NV_FOPT_RESET_PIN_CFG_SHIFT (3U)
|
|
#define NV_FOPT_RESET_PIN_CFG(x) \
|
|
(((uint8_t)(((uint8_t)(x)) << NV_FOPT_RESET_PIN_CFG_SHIFT)) & NV_FOPT_RESET_PIN_CFG_MASK)
|
|
#define NV_FOPT_LPBOOT1_MASK (0x10U)
|
|
#define NV_FOPT_LPBOOT1_SHIFT (4U)
|
|
#define NV_FOPT_LPBOOT1(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT1_SHIFT)) & NV_FOPT_LPBOOT1_MASK)
|
|
#define NV_FOPT_FAST_INIT_MASK (0x20U)
|
|
#define NV_FOPT_FAST_INIT_SHIFT (5U)
|
|
#define NV_FOPT_FAST_INIT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_FAST_INIT_SHIFT)) & NV_FOPT_FAST_INIT_MASK)
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group NV_Register_Masks */
|
|
|
|
/* NV - Peripheral instance base addresses */
|
|
/** Peripheral FTFA_FlashConfig base address */
|
|
#define FTFA_FlashConfig_BASE (0x400u)
|
|
/** Peripheral FTFA_FlashConfig base pointer */
|
|
#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
|
|
/** Array initializer of NV peripheral base addresses */
|
|
#define NV_BASE_ADDRS \
|
|
{ FTFA_FlashConfig_BASE }
|
|
/** Array initializer of NV peripheral base pointers */
|
|
#define NV_BASE_PTRS \
|
|
{ FTFA_FlashConfig }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group NV_Peripheral_Access_Layer */
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- OSC Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** OSC - Register Layout Typedef */
|
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typedef struct {
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__IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
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} OSC_Type;
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/* ----------------------------------------------------------------------------
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-- OSC Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup OSC_Register_Masks OSC Register Masks
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* @{
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*/
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/*! @name CR - OSC Control Register */
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#define OSC_CR_SC16P_MASK (0x1U)
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#define OSC_CR_SC16P_SHIFT (0U)
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#define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK)
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#define OSC_CR_SC8P_MASK (0x2U)
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#define OSC_CR_SC8P_SHIFT (1U)
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#define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK)
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#define OSC_CR_SC4P_MASK (0x4U)
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#define OSC_CR_SC4P_SHIFT (2U)
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#define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK)
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#define OSC_CR_SC2P_MASK (0x8U)
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#define OSC_CR_SC2P_SHIFT (3U)
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#define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK)
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#define OSC_CR_EREFSTEN_MASK (0x20U)
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#define OSC_CR_EREFSTEN_SHIFT (5U)
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#define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK)
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#define OSC_CR_ERCLKEN_MASK (0x80U)
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#define OSC_CR_ERCLKEN_SHIFT (7U)
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#define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK)
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/*!
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* @}
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*/ /* end of group OSC_Register_Masks */
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/* OSC - Peripheral instance base addresses */
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/** Peripheral OSC0 base address */
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#define OSC0_BASE (0x40065000u)
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/** Peripheral OSC0 base pointer */
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#define OSC0 ((OSC_Type *)OSC0_BASE)
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/** Array initializer of OSC peripheral base addresses */
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#define OSC_BASE_ADDRS \
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{ OSC0_BASE }
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/** Array initializer of OSC peripheral base pointers */
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#define OSC_BASE_PTRS \
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{ OSC0 }
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/*!
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* @}
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*/ /* end of group OSC_Peripheral_Access_Layer */
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/* ----------------------------------------------------------------------------
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-- PIT Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
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* @{
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*/
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/** PIT - Register Layout Typedef */
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typedef struct {
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__IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
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uint8_t RESERVED_0[220];
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__I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
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__I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
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uint8_t RESERVED_1[24];
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struct { /* offset: 0x100, array step: 0x10 */
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__IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
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__I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
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__IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
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__IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
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} CHANNEL[2];
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} PIT_Type;
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/* ----------------------------------------------------------------------------
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-- PIT Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup PIT_Register_Masks PIT Register Masks
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* @{
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*/
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/*! @name MCR - PIT Module Control Register */
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#define PIT_MCR_FRZ_MASK (0x1U)
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#define PIT_MCR_FRZ_SHIFT (0U)
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#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
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#define PIT_MCR_MDIS_MASK (0x2U)
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#define PIT_MCR_MDIS_SHIFT (1U)
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#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
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/*! @name LTMR64H - PIT Upper Lifetime Timer Register */
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#define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU)
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#define PIT_LTMR64H_LTH_SHIFT (0U)
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#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
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/*! @name LTMR64L - PIT Lower Lifetime Timer Register */
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#define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU)
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#define PIT_LTMR64L_LTL_SHIFT (0U)
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#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
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/*! @name LDVAL - Timer Load Value Register */
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#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
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#define PIT_LDVAL_TSV_SHIFT (0U)
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#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
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/* The count of PIT_LDVAL */
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#define PIT_LDVAL_COUNT (2U)
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/*! @name CVAL - Current Timer Value Register */
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#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
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#define PIT_CVAL_TVL_SHIFT (0U)
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#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
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/* The count of PIT_CVAL */
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#define PIT_CVAL_COUNT (2U)
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/*! @name TCTRL - Timer Control Register */
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#define PIT_TCTRL_TEN_MASK (0x1U)
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#define PIT_TCTRL_TEN_SHIFT (0U)
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#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
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#define PIT_TCTRL_TIE_MASK (0x2U)
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#define PIT_TCTRL_TIE_SHIFT (1U)
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#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
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#define PIT_TCTRL_CHN_MASK (0x4U)
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#define PIT_TCTRL_CHN_SHIFT (2U)
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#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
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/* The count of PIT_TCTRL */
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#define PIT_TCTRL_COUNT (2U)
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/*! @name TFLG - Timer Flag Register */
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#define PIT_TFLG_TIF_MASK (0x1U)
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#define PIT_TFLG_TIF_SHIFT (0U)
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#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
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/* The count of PIT_TFLG */
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#define PIT_TFLG_COUNT (2U)
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/*!
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* @}
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*/ /* end of group PIT_Register_Masks */
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/* PIT - Peripheral instance base addresses */
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/** Peripheral PIT base address */
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#define PIT_BASE (0x40037000u)
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/** Peripheral PIT base pointer */
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#define PIT ((PIT_Type *)PIT_BASE)
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/** Array initializer of PIT peripheral base addresses */
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#define PIT_BASE_ADDRS \
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{ PIT_BASE }
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/** Array initializer of PIT peripheral base pointers */
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#define PIT_BASE_PTRS \
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{ PIT }
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/** Interrupt vectors for the PIT peripheral type */
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#define PIT_IRQS \
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{ \
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{ PIT_IRQn, PIT_IRQn } \
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}
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/*!
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* @}
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*/ /* end of group PIT_Peripheral_Access_Layer */
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/* ----------------------------------------------------------------------------
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-- PMC Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
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* @{
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*/
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/** PMC - Register Layout Typedef */
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typedef struct {
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__IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
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__IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
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__IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
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} PMC_Type;
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/* ----------------------------------------------------------------------------
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-- PMC Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup PMC_Register_Masks PMC Register Masks
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* @{
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*/
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/*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
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#define PMC_LVDSC1_LVDV_MASK (0x3U)
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#define PMC_LVDSC1_LVDV_SHIFT (0U)
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#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
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#define PMC_LVDSC1_LVDRE_MASK (0x10U)
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#define PMC_LVDSC1_LVDRE_SHIFT (4U)
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#define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
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#define PMC_LVDSC1_LVDIE_MASK (0x20U)
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#define PMC_LVDSC1_LVDIE_SHIFT (5U)
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#define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
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#define PMC_LVDSC1_LVDACK_MASK (0x40U)
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#define PMC_LVDSC1_LVDACK_SHIFT (6U)
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#define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
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#define PMC_LVDSC1_LVDF_MASK (0x80U)
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#define PMC_LVDSC1_LVDF_SHIFT (7U)
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#define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
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/*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
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#define PMC_LVDSC2_LVWV_MASK (0x3U)
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#define PMC_LVDSC2_LVWV_SHIFT (0U)
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#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
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#define PMC_LVDSC2_LVWIE_MASK (0x20U)
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#define PMC_LVDSC2_LVWIE_SHIFT (5U)
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#define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
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#define PMC_LVDSC2_LVWACK_MASK (0x40U)
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#define PMC_LVDSC2_LVWACK_SHIFT (6U)
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#define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
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#define PMC_LVDSC2_LVWF_MASK (0x80U)
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#define PMC_LVDSC2_LVWF_SHIFT (7U)
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#define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
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/*! @name REGSC - Regulator Status And Control register */
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#define PMC_REGSC_BGBE_MASK (0x1U)
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#define PMC_REGSC_BGBE_SHIFT (0U)
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#define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
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#define PMC_REGSC_REGONS_MASK (0x4U)
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#define PMC_REGSC_REGONS_SHIFT (2U)
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#define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
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#define PMC_REGSC_ACKISO_MASK (0x8U)
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#define PMC_REGSC_ACKISO_SHIFT (3U)
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#define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
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#define PMC_REGSC_BGEN_MASK (0x10U)
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#define PMC_REGSC_BGEN_SHIFT (4U)
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#define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
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/*!
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* @}
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*/ /* end of group PMC_Register_Masks */
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/* PMC - Peripheral instance base addresses */
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/** Peripheral PMC base address */
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#define PMC_BASE (0x4007D000u)
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/** Peripheral PMC base pointer */
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#define PMC ((PMC_Type *)PMC_BASE)
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/** Array initializer of PMC peripheral base addresses */
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#define PMC_BASE_ADDRS \
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{ PMC_BASE }
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/** Array initializer of PMC peripheral base pointers */
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#define PMC_BASE_PTRS \
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{ PMC }
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/** Interrupt vectors for the PMC peripheral type */
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#define PMC_IRQS \
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{ LVD_LVW_IRQn }
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/*!
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* @}
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*/ /* end of group PMC_Peripheral_Access_Layer */
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/* ----------------------------------------------------------------------------
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-- PORT Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
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* @{
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*/
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/** PORT - Register Layout Typedef */
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typedef struct {
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__IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
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__O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
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__O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
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uint8_t RESERVED_0[24];
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__IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
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} PORT_Type;
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/* ----------------------------------------------------------------------------
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-- PORT Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup PORT_Register_Masks PORT Register Masks
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* @{
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*/
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/*! @name PCR - Pin Control Register n */
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#define PORT_PCR_PS_MASK (0x1U)
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#define PORT_PCR_PS_SHIFT (0U)
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#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
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#define PORT_PCR_PE_MASK (0x2U)
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#define PORT_PCR_PE_SHIFT (1U)
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#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
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#define PORT_PCR_SRE_MASK (0x4U)
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#define PORT_PCR_SRE_SHIFT (2U)
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#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
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#define PORT_PCR_PFE_MASK (0x10U)
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#define PORT_PCR_PFE_SHIFT (4U)
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#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
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#define PORT_PCR_DSE_MASK (0x40U)
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#define PORT_PCR_DSE_SHIFT (6U)
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#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
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#define PORT_PCR_MUX_MASK (0x700U)
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#define PORT_PCR_MUX_SHIFT (8U)
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#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
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#define PORT_PCR_IRQC_MASK (0xF0000U)
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#define PORT_PCR_IRQC_SHIFT (16U)
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#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
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#define PORT_PCR_ISF_MASK (0x1000000U)
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#define PORT_PCR_ISF_SHIFT (24U)
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#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
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/* The count of PORT_PCR */
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#define PORT_PCR_COUNT (32U)
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/*! @name GPCLR - Global Pin Control Low Register */
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#define PORT_GPCLR_GPWD_MASK (0xFFFFU)
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#define PORT_GPCLR_GPWD_SHIFT (0U)
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#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
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#define PORT_GPCLR_GPWE_MASK (0xFFFF0000U)
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#define PORT_GPCLR_GPWE_SHIFT (16U)
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#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
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/*! @name GPCHR - Global Pin Control High Register */
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#define PORT_GPCHR_GPWD_MASK (0xFFFFU)
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#define PORT_GPCHR_GPWD_SHIFT (0U)
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#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
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#define PORT_GPCHR_GPWE_MASK (0xFFFF0000U)
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#define PORT_GPCHR_GPWE_SHIFT (16U)
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#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
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/*! @name ISFR - Interrupt Status Flag Register */
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#define PORT_ISFR_ISF_MASK (0xFFFFFFFFU)
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#define PORT_ISFR_ISF_SHIFT (0U)
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#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
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/*!
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* @}
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*/ /* end of group PORT_Register_Masks */
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/* PORT - Peripheral instance base addresses */
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/** Peripheral PORTA base address */
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#define PORTA_BASE (0x40049000u)
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/** Peripheral PORTA base pointer */
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#define PORTA ((PORT_Type *)PORTA_BASE)
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/** Peripheral PORTB base address */
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#define PORTB_BASE (0x4004A000u)
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/** Peripheral PORTB base pointer */
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#define PORTB ((PORT_Type *)PORTB_BASE)
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/** Peripheral PORTC base address */
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#define PORTC_BASE (0x4004B000u)
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/** Peripheral PORTC base pointer */
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#define PORTC ((PORT_Type *)PORTC_BASE)
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/** Peripheral PORTD base address */
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#define PORTD_BASE (0x4004C000u)
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/** Peripheral PORTD base pointer */
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#define PORTD ((PORT_Type *)PORTD_BASE)
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|
/** Peripheral PORTE base address */
|
|
#define PORTE_BASE (0x4004D000u)
|
|
/** Peripheral PORTE base pointer */
|
|
#define PORTE ((PORT_Type *)PORTE_BASE)
|
|
/** Array initializer of PORT peripheral base addresses */
|
|
#define PORT_BASE_ADDRS \
|
|
{ PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
|
|
/** Array initializer of PORT peripheral base pointers */
|
|
#define PORT_BASE_PTRS \
|
|
{ PORTA, PORTB, PORTC, PORTD, PORTE }
|
|
/** Interrupt vectors for the PORT peripheral type */
|
|
#define PORT_IRQS \
|
|
{ PORTA_IRQn, NotAvail_IRQn, NotAvail_IRQn, PORTD_IRQn, NotAvail_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group PORT_Peripheral_Access_Layer */
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- RCM Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** RCM - Register Layout Typedef */
|
|
typedef struct {
|
|
__I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
|
|
__I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
|
|
uint8_t RESERVED_0[2];
|
|
__IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
|
|
__IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
|
|
} RCM_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- RCM Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup RCM_Register_Masks RCM Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name SRS0 - System Reset Status Register 0 */
|
|
#define RCM_SRS0_WAKEUP_MASK (0x1U)
|
|
#define RCM_SRS0_WAKEUP_SHIFT (0U)
|
|
#define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
|
|
#define RCM_SRS0_LVD_MASK (0x2U)
|
|
#define RCM_SRS0_LVD_SHIFT (1U)
|
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#define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
|
|
#define RCM_SRS0_LOC_MASK (0x4U)
|
|
#define RCM_SRS0_LOC_SHIFT (2U)
|
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#define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
|
|
#define RCM_SRS0_LOL_MASK (0x8U)
|
|
#define RCM_SRS0_LOL_SHIFT (3U)
|
|
#define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK)
|
|
#define RCM_SRS0_WDOG_MASK (0x20U)
|
|
#define RCM_SRS0_WDOG_SHIFT (5U)
|
|
#define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
|
|
#define RCM_SRS0_PIN_MASK (0x40U)
|
|
#define RCM_SRS0_PIN_SHIFT (6U)
|
|
#define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
|
|
#define RCM_SRS0_POR_MASK (0x80U)
|
|
#define RCM_SRS0_POR_SHIFT (7U)
|
|
#define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
|
|
|
|
/*! @name SRS1 - System Reset Status Register 1 */
|
|
#define RCM_SRS1_LOCKUP_MASK (0x2U)
|
|
#define RCM_SRS1_LOCKUP_SHIFT (1U)
|
|
#define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
|
|
#define RCM_SRS1_SW_MASK (0x4U)
|
|
#define RCM_SRS1_SW_SHIFT (2U)
|
|
#define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
|
|
#define RCM_SRS1_MDM_AP_MASK (0x8U)
|
|
#define RCM_SRS1_MDM_AP_SHIFT (3U)
|
|
#define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
|
|
#define RCM_SRS1_SACKERR_MASK (0x20U)
|
|
#define RCM_SRS1_SACKERR_SHIFT (5U)
|
|
#define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
|
|
|
|
/*! @name RPFC - Reset Pin Filter Control register */
|
|
#define RCM_RPFC_RSTFLTSRW_MASK (0x3U)
|
|
#define RCM_RPFC_RSTFLTSRW_SHIFT (0U)
|
|
#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
|
|
#define RCM_RPFC_RSTFLTSS_MASK (0x4U)
|
|
#define RCM_RPFC_RSTFLTSS_SHIFT (2U)
|
|
#define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
|
|
|
|
/*! @name RPFW - Reset Pin Filter Width register */
|
|
#define RCM_RPFW_RSTFLTSEL_MASK (0x1FU)
|
|
#define RCM_RPFW_RSTFLTSEL_SHIFT (0U)
|
|
#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group RCM_Register_Masks */
|
|
|
|
/* RCM - Peripheral instance base addresses */
|
|
/** Peripheral RCM base address */
|
|
#define RCM_BASE (0x4007F000u)
|
|
/** Peripheral RCM base pointer */
|
|
#define RCM ((RCM_Type *)RCM_BASE)
|
|
/** Array initializer of RCM peripheral base addresses */
|
|
#define RCM_BASE_ADDRS \
|
|
{ RCM_BASE }
|
|
/** Array initializer of RCM peripheral base pointers */
|
|
#define RCM_BASE_PTRS \
|
|
{ RCM }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group RCM_Peripheral_Access_Layer */
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- ROM Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** ROM - Register Layout Typedef */
|
|
typedef struct {
|
|
__I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
|
|
__I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
|
|
uint8_t RESERVED_0[4028];
|
|
__I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
|
|
__I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
|
|
__I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
|
|
__I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
|
|
__I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
|
|
__I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
|
|
__I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
|
|
__I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
|
|
__I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
|
|
__I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
|
|
} ROM_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- ROM Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup ROM_Register_Masks ROM Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name ENTRY - Entry */
|
|
#define ROM_ENTRY_ENTRY_MASK (0xFFFFFFFFU)
|
|
#define ROM_ENTRY_ENTRY_SHIFT (0U)
|
|
#define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x)) << ROM_ENTRY_ENTRY_SHIFT)) & ROM_ENTRY_ENTRY_MASK)
|
|
|
|
/* The count of ROM_ENTRY */
|
|
#define ROM_ENTRY_COUNT (3U)
|
|
|
|
/*! @name TABLEMARK - End of Table Marker Register */
|
|
#define ROM_TABLEMARK_MARK_MASK (0xFFFFFFFFU)
|
|
#define ROM_TABLEMARK_MARK_SHIFT (0U)
|
|
#define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x)) << ROM_TABLEMARK_MARK_SHIFT)) & ROM_TABLEMARK_MARK_MASK)
|
|
|
|
/*! @name SYSACCESS - System Access Register */
|
|
#define ROM_SYSACCESS_SYSACCESS_MASK (0xFFFFFFFFU)
|
|
#define ROM_SYSACCESS_SYSACCESS_SHIFT (0U)
|
|
#define ROM_SYSACCESS_SYSACCESS(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << ROM_SYSACCESS_SYSACCESS_SHIFT)) & ROM_SYSACCESS_SYSACCESS_MASK)
|
|
|
|
/*! @name PERIPHID4 - Peripheral ID Register */
|
|
#define ROM_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU)
|
|
#define ROM_PERIPHID4_PERIPHID_SHIFT (0U)
|
|
#define ROM_PERIPHID4_PERIPHID(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID4_PERIPHID_SHIFT)) & ROM_PERIPHID4_PERIPHID_MASK)
|
|
|
|
/*! @name PERIPHID5 - Peripheral ID Register */
|
|
#define ROM_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU)
|
|
#define ROM_PERIPHID5_PERIPHID_SHIFT (0U)
|
|
#define ROM_PERIPHID5_PERIPHID(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID5_PERIPHID_SHIFT)) & ROM_PERIPHID5_PERIPHID_MASK)
|
|
|
|
/*! @name PERIPHID6 - Peripheral ID Register */
|
|
#define ROM_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU)
|
|
#define ROM_PERIPHID6_PERIPHID_SHIFT (0U)
|
|
#define ROM_PERIPHID6_PERIPHID(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID6_PERIPHID_SHIFT)) & ROM_PERIPHID6_PERIPHID_MASK)
|
|
|
|
/*! @name PERIPHID7 - Peripheral ID Register */
|
|
#define ROM_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU)
|
|
#define ROM_PERIPHID7_PERIPHID_SHIFT (0U)
|
|
#define ROM_PERIPHID7_PERIPHID(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID7_PERIPHID_SHIFT)) & ROM_PERIPHID7_PERIPHID_MASK)
|
|
|
|
/*! @name PERIPHID0 - Peripheral ID Register */
|
|
#define ROM_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU)
|
|
#define ROM_PERIPHID0_PERIPHID_SHIFT (0U)
|
|
#define ROM_PERIPHID0_PERIPHID(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID0_PERIPHID_SHIFT)) & ROM_PERIPHID0_PERIPHID_MASK)
|
|
|
|
/*! @name PERIPHID1 - Peripheral ID Register */
|
|
#define ROM_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU)
|
|
#define ROM_PERIPHID1_PERIPHID_SHIFT (0U)
|
|
#define ROM_PERIPHID1_PERIPHID(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID1_PERIPHID_SHIFT)) & ROM_PERIPHID1_PERIPHID_MASK)
|
|
|
|
/*! @name PERIPHID2 - Peripheral ID Register */
|
|
#define ROM_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU)
|
|
#define ROM_PERIPHID2_PERIPHID_SHIFT (0U)
|
|
#define ROM_PERIPHID2_PERIPHID(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID2_PERIPHID_SHIFT)) & ROM_PERIPHID2_PERIPHID_MASK)
|
|
|
|
/*! @name PERIPHID3 - Peripheral ID Register */
|
|
#define ROM_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU)
|
|
#define ROM_PERIPHID3_PERIPHID_SHIFT (0U)
|
|
#define ROM_PERIPHID3_PERIPHID(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID3_PERIPHID_SHIFT)) & ROM_PERIPHID3_PERIPHID_MASK)
|
|
|
|
/*! @name COMPID - Component ID Register */
|
|
#define ROM_COMPID_COMPID_MASK (0xFFFFFFFFU)
|
|
#define ROM_COMPID_COMPID_SHIFT (0U)
|
|
#define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << ROM_COMPID_COMPID_SHIFT)) & ROM_COMPID_COMPID_MASK)
|
|
|
|
/* The count of ROM_COMPID */
|
|
#define ROM_COMPID_COUNT (4U)
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group ROM_Register_Masks */
|
|
|
|
/* ROM - Peripheral instance base addresses */
|
|
/** Peripheral ROM base address */
|
|
#define ROM_BASE (0xF0002000u)
|
|
/** Peripheral ROM base pointer */
|
|
#define ROM ((ROM_Type *)ROM_BASE)
|
|
/** Array initializer of ROM peripheral base addresses */
|
|
#define ROM_BASE_ADDRS \
|
|
{ ROM_BASE }
|
|
/** Array initializer of ROM peripheral base pointers */
|
|
#define ROM_BASE_PTRS \
|
|
{ ROM }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group ROM_Peripheral_Access_Layer */
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- RTC Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** RTC - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
|
|
__IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
|
|
__IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
|
|
__IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
|
|
__IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
|
|
__IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
|
|
__IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
|
|
__IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
|
|
} RTC_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- RTC Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup RTC_Register_Masks RTC Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name TSR - RTC Time Seconds Register */
|
|
#define RTC_TSR_TSR_MASK (0xFFFFFFFFU)
|
|
#define RTC_TSR_TSR_SHIFT (0U)
|
|
#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
|
|
|
|
/*! @name TPR - RTC Time Prescaler Register */
|
|
#define RTC_TPR_TPR_MASK (0xFFFFU)
|
|
#define RTC_TPR_TPR_SHIFT (0U)
|
|
#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
|
|
|
|
/*! @name TAR - RTC Time Alarm Register */
|
|
#define RTC_TAR_TAR_MASK (0xFFFFFFFFU)
|
|
#define RTC_TAR_TAR_SHIFT (0U)
|
|
#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
|
|
|
|
/*! @name TCR - RTC Time Compensation Register */
|
|
#define RTC_TCR_TCR_MASK (0xFFU)
|
|
#define RTC_TCR_TCR_SHIFT (0U)
|
|
#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
|
|
#define RTC_TCR_CIR_MASK (0xFF00U)
|
|
#define RTC_TCR_CIR_SHIFT (8U)
|
|
#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
|
|
#define RTC_TCR_TCV_MASK (0xFF0000U)
|
|
#define RTC_TCR_TCV_SHIFT (16U)
|
|
#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
|
|
#define RTC_TCR_CIC_MASK (0xFF000000U)
|
|
#define RTC_TCR_CIC_SHIFT (24U)
|
|
#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
|
|
|
|
/*! @name CR - RTC Control Register */
|
|
#define RTC_CR_SWR_MASK (0x1U)
|
|
#define RTC_CR_SWR_SHIFT (0U)
|
|
#define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
|
|
#define RTC_CR_WPE_MASK (0x2U)
|
|
#define RTC_CR_WPE_SHIFT (1U)
|
|
#define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
|
|
#define RTC_CR_SUP_MASK (0x4U)
|
|
#define RTC_CR_SUP_SHIFT (2U)
|
|
#define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
|
|
#define RTC_CR_UM_MASK (0x8U)
|
|
#define RTC_CR_UM_SHIFT (3U)
|
|
#define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
|
|
#define RTC_CR_OSCE_MASK (0x100U)
|
|
#define RTC_CR_OSCE_SHIFT (8U)
|
|
#define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
|
|
#define RTC_CR_CLKO_MASK (0x200U)
|
|
#define RTC_CR_CLKO_SHIFT (9U)
|
|
#define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
|
|
#define RTC_CR_SC16P_MASK (0x400U)
|
|
#define RTC_CR_SC16P_SHIFT (10U)
|
|
#define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
|
|
#define RTC_CR_SC8P_MASK (0x800U)
|
|
#define RTC_CR_SC8P_SHIFT (11U)
|
|
#define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
|
|
#define RTC_CR_SC4P_MASK (0x1000U)
|
|
#define RTC_CR_SC4P_SHIFT (12U)
|
|
#define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
|
|
#define RTC_CR_SC2P_MASK (0x2000U)
|
|
#define RTC_CR_SC2P_SHIFT (13U)
|
|
#define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
|
|
|
|
/*! @name SR - RTC Status Register */
|
|
#define RTC_SR_TIF_MASK (0x1U)
|
|
#define RTC_SR_TIF_SHIFT (0U)
|
|
#define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
|
|
#define RTC_SR_TOF_MASK (0x2U)
|
|
#define RTC_SR_TOF_SHIFT (1U)
|
|
#define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
|
|
#define RTC_SR_TAF_MASK (0x4U)
|
|
#define RTC_SR_TAF_SHIFT (2U)
|
|
#define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
|
|
#define RTC_SR_TCE_MASK (0x10U)
|
|
#define RTC_SR_TCE_SHIFT (4U)
|
|
#define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
|
|
|
|
/*! @name LR - RTC Lock Register */
|
|
#define RTC_LR_TCL_MASK (0x8U)
|
|
#define RTC_LR_TCL_SHIFT (3U)
|
|
#define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
|
|
#define RTC_LR_CRL_MASK (0x10U)
|
|
#define RTC_LR_CRL_SHIFT (4U)
|
|
#define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
|
|
#define RTC_LR_SRL_MASK (0x20U)
|
|
#define RTC_LR_SRL_SHIFT (5U)
|
|
#define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
|
|
#define RTC_LR_LRL_MASK (0x40U)
|
|
#define RTC_LR_LRL_SHIFT (6U)
|
|
#define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
|
|
|
|
/*! @name IER - RTC Interrupt Enable Register */
|
|
#define RTC_IER_TIIE_MASK (0x1U)
|
|
#define RTC_IER_TIIE_SHIFT (0U)
|
|
#define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
|
|
#define RTC_IER_TOIE_MASK (0x2U)
|
|
#define RTC_IER_TOIE_SHIFT (1U)
|
|
#define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
|
|
#define RTC_IER_TAIE_MASK (0x4U)
|
|
#define RTC_IER_TAIE_SHIFT (2U)
|
|
#define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
|
|
#define RTC_IER_TSIE_MASK (0x10U)
|
|
#define RTC_IER_TSIE_SHIFT (4U)
|
|
#define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
|
|
#define RTC_IER_WPON_MASK (0x80U)
|
|
#define RTC_IER_WPON_SHIFT (7U)
|
|
#define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group RTC_Register_Masks */
|
|
|
|
/* RTC - Peripheral instance base addresses */
|
|
/** Peripheral RTC base address */
|
|
#define RTC_BASE (0x4003D000u)
|
|
/** Peripheral RTC base pointer */
|
|
#define RTC ((RTC_Type *)RTC_BASE)
|
|
/** Array initializer of RTC peripheral base addresses */
|
|
#define RTC_BASE_ADDRS \
|
|
{ RTC_BASE }
|
|
/** Array initializer of RTC peripheral base pointers */
|
|
#define RTC_BASE_PTRS \
|
|
{ RTC }
|
|
/** Interrupt vectors for the RTC peripheral type */
|
|
#define RTC_IRQS \
|
|
{ RTC_IRQn }
|
|
#define RTC_SECONDS_IRQS \
|
|
{ RTC_Seconds_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group RTC_Peripheral_Access_Layer */
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- SIM Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** SIM - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
|
|
__IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
|
|
uint8_t RESERVED_0[4092];
|
|
__IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
|
|
uint8_t RESERVED_1[4];
|
|
__IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
|
|
__IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
|
|
uint8_t RESERVED_2[4];
|
|
__IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
|
|
uint8_t RESERVED_3[8];
|
|
__I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
|
|
uint8_t RESERVED_4[12];
|
|
__IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
|
|
__IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
|
|
__IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
|
|
__IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
|
|
__IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
|
|
uint8_t RESERVED_5[4];
|
|
__IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
|
|
__I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
|
|
uint8_t RESERVED_6[4];
|
|
__I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
|
|
__I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
|
|
__I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
|
|
uint8_t RESERVED_7[156];
|
|
__IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
|
|
__O uint32_t SRVCOP; /**< Service COP Register, offset: 0x1104 */
|
|
} SIM_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- SIM Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup SIM_Register_Masks SIM Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name SOPT1 - System Options Register 1 */
|
|
#define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U)
|
|
#define SIM_SOPT1_OSC32KSEL_SHIFT (18U)
|
|
#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
|
|
#define SIM_SOPT1_USBVSTBY_MASK (0x20000000U)
|
|
#define SIM_SOPT1_USBVSTBY_SHIFT (29U)
|
|
#define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)
|
|
#define SIM_SOPT1_USBSSTBY_MASK (0x40000000U)
|
|
#define SIM_SOPT1_USBSSTBY_SHIFT (30U)
|
|
#define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
|
|
#define SIM_SOPT1_USBREGEN_MASK (0x80000000U)
|
|
#define SIM_SOPT1_USBREGEN_SHIFT (31U)
|
|
#define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
|
|
|
|
/*! @name SOPT1CFG - SOPT1 Configuration Register */
|
|
#define SIM_SOPT1CFG_URWE_MASK (0x1000000U)
|
|
#define SIM_SOPT1CFG_URWE_SHIFT (24U)
|
|
#define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
|
|
#define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U)
|
|
#define SIM_SOPT1CFG_UVSWE_SHIFT (25U)
|
|
#define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)
|
|
#define SIM_SOPT1CFG_USSWE_MASK (0x4000000U)
|
|
#define SIM_SOPT1CFG_USSWE_SHIFT (26U)
|
|
#define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)
|
|
|
|
/*! @name SOPT2 - System Options Register 2 */
|
|
#define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U)
|
|
#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U)
|
|
#define SIM_SOPT2_RTCCLKOUTSEL(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
|
|
#define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U)
|
|
#define SIM_SOPT2_CLKOUTSEL_SHIFT (5U)
|
|
#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
|
|
#define SIM_SOPT2_PLLFLLSEL_MASK (0x10000U)
|
|
#define SIM_SOPT2_PLLFLLSEL_SHIFT (16U)
|
|
#define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
|
|
#define SIM_SOPT2_USBSRC_MASK (0x40000U)
|
|
#define SIM_SOPT2_USBSRC_SHIFT (18U)
|
|
#define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)
|
|
#define SIM_SOPT2_TPMSRC_MASK (0x3000000U)
|
|
#define SIM_SOPT2_TPMSRC_SHIFT (24U)
|
|
#define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TPMSRC_SHIFT)) & SIM_SOPT2_TPMSRC_MASK)
|
|
#define SIM_SOPT2_UART0SRC_MASK (0xC000000U)
|
|
#define SIM_SOPT2_UART0SRC_SHIFT (26U)
|
|
#define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_UART0SRC_SHIFT)) & SIM_SOPT2_UART0SRC_MASK)
|
|
|
|
/*! @name SOPT4 - System Options Register 4 */
|
|
#define SIM_SOPT4_TPM1CH0SRC_MASK (0x40000U)
|
|
#define SIM_SOPT4_TPM1CH0SRC_SHIFT (18U)
|
|
#define SIM_SOPT4_TPM1CH0SRC(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM1CH0SRC_SHIFT)) & SIM_SOPT4_TPM1CH0SRC_MASK)
|
|
#define SIM_SOPT4_TPM2CH0SRC_MASK (0x100000U)
|
|
#define SIM_SOPT4_TPM2CH0SRC_SHIFT (20U)
|
|
#define SIM_SOPT4_TPM2CH0SRC(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM2CH0SRC_SHIFT)) & SIM_SOPT4_TPM2CH0SRC_MASK)
|
|
#define SIM_SOPT4_TPM0CLKSEL_MASK (0x1000000U)
|
|
#define SIM_SOPT4_TPM0CLKSEL_SHIFT (24U)
|
|
#define SIM_SOPT4_TPM0CLKSEL(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM0CLKSEL_SHIFT)) & SIM_SOPT4_TPM0CLKSEL_MASK)
|
|
#define SIM_SOPT4_TPM1CLKSEL_MASK (0x2000000U)
|
|
#define SIM_SOPT4_TPM1CLKSEL_SHIFT (25U)
|
|
#define SIM_SOPT4_TPM1CLKSEL(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM1CLKSEL_SHIFT)) & SIM_SOPT4_TPM1CLKSEL_MASK)
|
|
#define SIM_SOPT4_TPM2CLKSEL_MASK (0x4000000U)
|
|
#define SIM_SOPT4_TPM2CLKSEL_SHIFT (26U)
|
|
#define SIM_SOPT4_TPM2CLKSEL(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM2CLKSEL_SHIFT)) & SIM_SOPT4_TPM2CLKSEL_MASK)
|
|
|
|
/*! @name SOPT5 - System Options Register 5 */
|
|
#define SIM_SOPT5_UART0TXSRC_MASK (0x3U)
|
|
#define SIM_SOPT5_UART0TXSRC_SHIFT (0U)
|
|
#define SIM_SOPT5_UART0TXSRC(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
|
|
#define SIM_SOPT5_UART0RXSRC_MASK (0x4U)
|
|
#define SIM_SOPT5_UART0RXSRC_SHIFT (2U)
|
|
#define SIM_SOPT5_UART0RXSRC(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
|
|
#define SIM_SOPT5_UART1TXSRC_MASK (0x30U)
|
|
#define SIM_SOPT5_UART1TXSRC_SHIFT (4U)
|
|
#define SIM_SOPT5_UART1TXSRC(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
|
|
#define SIM_SOPT5_UART1RXSRC_MASK (0x40U)
|
|
#define SIM_SOPT5_UART1RXSRC_SHIFT (6U)
|
|
#define SIM_SOPT5_UART1RXSRC(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
|
|
#define SIM_SOPT5_UART0ODE_MASK (0x10000U)
|
|
#define SIM_SOPT5_UART0ODE_SHIFT (16U)
|
|
#define SIM_SOPT5_UART0ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0ODE_SHIFT)) & SIM_SOPT5_UART0ODE_MASK)
|
|
#define SIM_SOPT5_UART1ODE_MASK (0x20000U)
|
|
#define SIM_SOPT5_UART1ODE_SHIFT (17U)
|
|
#define SIM_SOPT5_UART1ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1ODE_SHIFT)) & SIM_SOPT5_UART1ODE_MASK)
|
|
#define SIM_SOPT5_UART2ODE_MASK (0x40000U)
|
|
#define SIM_SOPT5_UART2ODE_SHIFT (18U)
|
|
#define SIM_SOPT5_UART2ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART2ODE_SHIFT)) & SIM_SOPT5_UART2ODE_MASK)
|
|
|
|
/*! @name SOPT7 - System Options Register 7 */
|
|
#define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU)
|
|
#define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U)
|
|
#define SIM_SOPT7_ADC0TRGSEL(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
|
|
#define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U)
|
|
#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U)
|
|
#define SIM_SOPT7_ADC0PRETRGSEL(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
|
|
#define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U)
|
|
#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U)
|
|
#define SIM_SOPT7_ADC0ALTTRGEN(x) \
|
|
(((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
|
|
|
|
/*! @name SDID - System Device Identification Register */
|
|
#define SIM_SDID_PINID_MASK (0xFU)
|
|
#define SIM_SDID_PINID_SHIFT (0U)
|
|
#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
|
|
#define SIM_SDID_DIEID_MASK (0xF80U)
|
|
#define SIM_SDID_DIEID_SHIFT (7U)
|
|
#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
|
|
#define SIM_SDID_REVID_MASK (0xF000U)
|
|
#define SIM_SDID_REVID_SHIFT (12U)
|
|
#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
|
|
#define SIM_SDID_SRAMSIZE_MASK (0xF0000U)
|
|
#define SIM_SDID_SRAMSIZE_SHIFT (16U)
|
|
#define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SRAMSIZE_SHIFT)) & SIM_SDID_SRAMSIZE_MASK)
|
|
#define SIM_SDID_SERIESID_MASK (0xF00000U)
|
|
#define SIM_SDID_SERIESID_SHIFT (20U)
|
|
#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
|
|
#define SIM_SDID_SUBFAMID_MASK (0xF000000U)
|
|
#define SIM_SDID_SUBFAMID_SHIFT (24U)
|
|
#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
|
|
#define SIM_SDID_FAMID_MASK (0xF0000000U)
|
|
#define SIM_SDID_FAMID_SHIFT (28U)
|
|
#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
|
|
|
|
/*! @name SCGC4 - System Clock Gating Control Register 4 */
|
|
#define SIM_SCGC4_I2C0_MASK (0x40U)
|
|
#define SIM_SCGC4_I2C0_SHIFT (6U)
|
|
#define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
|
|
#define SIM_SCGC4_I2C1_MASK (0x80U)
|
|
#define SIM_SCGC4_I2C1_SHIFT (7U)
|
|
#define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
|
|
#define SIM_SCGC4_UART0_MASK (0x400U)
|
|
#define SIM_SCGC4_UART0_SHIFT (10U)
|
|
#define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
|
|
#define SIM_SCGC4_UART1_MASK (0x800U)
|
|
#define SIM_SCGC4_UART1_SHIFT (11U)
|
|
#define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
|
|
#define SIM_SCGC4_UART2_MASK (0x1000U)
|
|
#define SIM_SCGC4_UART2_SHIFT (12U)
|
|
#define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
|
|
#define SIM_SCGC4_USBOTG_MASK (0x40000U)
|
|
#define SIM_SCGC4_USBOTG_SHIFT (18U)
|
|
#define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)
|
|
#define SIM_SCGC4_CMP_MASK (0x80000U)
|
|
#define SIM_SCGC4_CMP_SHIFT (19U)
|
|
#define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
|
|
#define SIM_SCGC4_SPI0_MASK (0x400000U)
|
|
#define SIM_SCGC4_SPI0_SHIFT (22U)
|
|
#define SIM_SCGC4_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_SPI0_SHIFT)) & SIM_SCGC4_SPI0_MASK)
|
|
#define SIM_SCGC4_SPI1_MASK (0x800000U)
|
|
#define SIM_SCGC4_SPI1_SHIFT (23U)
|
|
#define SIM_SCGC4_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_SPI1_SHIFT)) & SIM_SCGC4_SPI1_MASK)
|
|
|
|
/*! @name SCGC5 - System Clock Gating Control Register 5 */
|
|
#define SIM_SCGC5_LPTMR_MASK (0x1U)
|
|
#define SIM_SCGC5_LPTMR_SHIFT (0U)
|
|
#define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
|
|
#define SIM_SCGC5_TSI_MASK (0x20U)
|
|
#define SIM_SCGC5_TSI_SHIFT (5U)
|
|
#define SIM_SCGC5_TSI(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)
|
|
#define SIM_SCGC5_PORTA_MASK (0x200U)
|
|
#define SIM_SCGC5_PORTA_SHIFT (9U)
|
|
#define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
|
|
#define SIM_SCGC5_PORTB_MASK (0x400U)
|
|
#define SIM_SCGC5_PORTB_SHIFT (10U)
|
|
#define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
|
|
#define SIM_SCGC5_PORTC_MASK (0x800U)
|
|
#define SIM_SCGC5_PORTC_SHIFT (11U)
|
|
#define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
|
|
#define SIM_SCGC5_PORTD_MASK (0x1000U)
|
|
#define SIM_SCGC5_PORTD_SHIFT (12U)
|
|
#define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
|
|
#define SIM_SCGC5_PORTE_MASK (0x2000U)
|
|
#define SIM_SCGC5_PORTE_SHIFT (13U)
|
|
#define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
|
|
|
|
/*! @name SCGC6 - System Clock Gating Control Register 6 */
|
|
#define SIM_SCGC6_FTF_MASK (0x1U)
|
|
#define SIM_SCGC6_FTF_SHIFT (0U)
|
|
#define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
|
|
#define SIM_SCGC6_DMAMUX_MASK (0x2U)
|
|
#define SIM_SCGC6_DMAMUX_SHIFT (1U)
|
|
#define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
|
|
#define SIM_SCGC6_PIT_MASK (0x800000U)
|
|
#define SIM_SCGC6_PIT_SHIFT (23U)
|
|
#define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
|
|
#define SIM_SCGC6_TPM0_MASK (0x1000000U)
|
|
#define SIM_SCGC6_TPM0_SHIFT (24U)
|
|
#define SIM_SCGC6_TPM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM0_SHIFT)) & SIM_SCGC6_TPM0_MASK)
|
|
#define SIM_SCGC6_TPM1_MASK (0x2000000U)
|
|
#define SIM_SCGC6_TPM1_SHIFT (25U)
|
|
#define SIM_SCGC6_TPM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM1_SHIFT)) & SIM_SCGC6_TPM1_MASK)
|
|
#define SIM_SCGC6_TPM2_MASK (0x4000000U)
|
|
#define SIM_SCGC6_TPM2_SHIFT (26U)
|
|
#define SIM_SCGC6_TPM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM2_SHIFT)) & SIM_SCGC6_TPM2_MASK)
|
|
#define SIM_SCGC6_ADC0_MASK (0x8000000U)
|
|
#define SIM_SCGC6_ADC0_SHIFT (27U)
|
|
#define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
|
|
#define SIM_SCGC6_RTC_MASK (0x20000000U)
|
|
#define SIM_SCGC6_RTC_SHIFT (29U)
|
|
#define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
|
|
#define SIM_SCGC6_DAC0_MASK (0x80000000U)
|
|
#define SIM_SCGC6_DAC0_SHIFT (31U)
|
|
#define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
|
|
|
|
/*! @name SCGC7 - System Clock Gating Control Register 7 */
|
|
#define SIM_SCGC7_DMA_MASK (0x100U)
|
|
#define SIM_SCGC7_DMA_SHIFT (8U)
|
|
#define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
|
|
|
|
/*! @name CLKDIV1 - System Clock Divider Register 1 */
|
|
#define SIM_CLKDIV1_OUTDIV4_MASK (0x70000U)
|
|
#define SIM_CLKDIV1_OUTDIV4_SHIFT (16U)
|
|
#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
|
|
#define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U)
|
|
#define SIM_CLKDIV1_OUTDIV1_SHIFT (28U)
|
|
#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
|
|
|
|
/*! @name FCFG1 - Flash Configuration Register 1 */
|
|
#define SIM_FCFG1_FLASHDIS_MASK (0x1U)
|
|
#define SIM_FCFG1_FLASHDIS_SHIFT (0U)
|
|
#define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
|
|
#define SIM_FCFG1_FLASHDOZE_MASK (0x2U)
|
|
#define SIM_FCFG1_FLASHDOZE_SHIFT (1U)
|
|
#define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
|
|
#define SIM_FCFG1_PFSIZE_MASK (0xF000000U)
|
|
#define SIM_FCFG1_PFSIZE_SHIFT (24U)
|
|
#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
|
|
|
|
/*! @name FCFG2 - Flash Configuration Register 2 */
|
|
#define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U)
|
|
#define SIM_FCFG2_MAXADDR0_SHIFT (24U)
|
|
#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
|
|
|
|
/*! @name UIDMH - Unique Identification Register Mid-High */
|
|
#define SIM_UIDMH_UID_MASK (0xFFFFU)
|
|
#define SIM_UIDMH_UID_SHIFT (0U)
|
|
#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
|
|
|
|
/*! @name UIDML - Unique Identification Register Mid Low */
|
|
#define SIM_UIDML_UID_MASK (0xFFFFFFFFU)
|
|
#define SIM_UIDML_UID_SHIFT (0U)
|
|
#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
|
|
|
|
/*! @name UIDL - Unique Identification Register Low */
|
|
#define SIM_UIDL_UID_MASK (0xFFFFFFFFU)
|
|
#define SIM_UIDL_UID_SHIFT (0U)
|
|
#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
|
|
|
|
/*! @name COPC - COP Control Register */
|
|
#define SIM_COPC_COPW_MASK (0x1U)
|
|
#define SIM_COPC_COPW_SHIFT (0U)
|
|
#define SIM_COPC_COPW(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPW_SHIFT)) & SIM_COPC_COPW_MASK)
|
|
#define SIM_COPC_COPCLKS_MASK (0x2U)
|
|
#define SIM_COPC_COPCLKS_SHIFT (1U)
|
|
#define SIM_COPC_COPCLKS(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPCLKS_SHIFT)) & SIM_COPC_COPCLKS_MASK)
|
|
#define SIM_COPC_COPT_MASK (0xCU)
|
|
#define SIM_COPC_COPT_SHIFT (2U)
|
|
#define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPT_SHIFT)) & SIM_COPC_COPT_MASK)
|
|
|
|
/*! @name SRVCOP - Service COP Register */
|
|
#define SIM_SRVCOP_SRVCOP_MASK (0xFFU)
|
|
#define SIM_SRVCOP_SRVCOP_SHIFT (0U)
|
|
#define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRVCOP_SRVCOP_SHIFT)) & SIM_SRVCOP_SRVCOP_MASK)
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group SIM_Register_Masks */
|
|
|
|
/* SIM - Peripheral instance base addresses */
|
|
/** Peripheral SIM base address */
|
|
#define SIM_BASE (0x40047000u)
|
|
/** Peripheral SIM base pointer */
|
|
#define SIM ((SIM_Type *)SIM_BASE)
|
|
/** Array initializer of SIM peripheral base addresses */
|
|
#define SIM_BASE_ADDRS \
|
|
{ SIM_BASE }
|
|
/** Array initializer of SIM peripheral base pointers */
|
|
#define SIM_BASE_PTRS \
|
|
{ SIM }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group SIM_Peripheral_Access_Layer */
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- SMC Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** SMC - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
|
|
__IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
|
|
__IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
|
|
__I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
|
|
} SMC_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- SMC Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup SMC_Register_Masks SMC Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name PMPROT - Power Mode Protection register */
|
|
#define SMC_PMPROT_AVLLS_MASK (0x2U)
|
|
#define SMC_PMPROT_AVLLS_SHIFT (1U)
|
|
#define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
|
|
#define SMC_PMPROT_ALLS_MASK (0x8U)
|
|
#define SMC_PMPROT_ALLS_SHIFT (3U)
|
|
#define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
|
|
#define SMC_PMPROT_AVLP_MASK (0x20U)
|
|
#define SMC_PMPROT_AVLP_SHIFT (5U)
|
|
#define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
|
|
|
|
/*! @name PMCTRL - Power Mode Control register */
|
|
#define SMC_PMCTRL_STOPM_MASK (0x7U)
|
|
#define SMC_PMCTRL_STOPM_SHIFT (0U)
|
|
#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
|
|
#define SMC_PMCTRL_STOPA_MASK (0x8U)
|
|
#define SMC_PMCTRL_STOPA_SHIFT (3U)
|
|
#define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
|
|
#define SMC_PMCTRL_RUNM_MASK (0x60U)
|
|
#define SMC_PMCTRL_RUNM_SHIFT (5U)
|
|
#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
|
|
|
|
/*! @name STOPCTRL - Stop Control Register */
|
|
#define SMC_STOPCTRL_VLLSM_MASK (0x7U)
|
|
#define SMC_STOPCTRL_VLLSM_SHIFT (0U)
|
|
#define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_VLLSM_SHIFT)) & SMC_STOPCTRL_VLLSM_MASK)
|
|
#define SMC_STOPCTRL_PORPO_MASK (0x20U)
|
|
#define SMC_STOPCTRL_PORPO_SHIFT (5U)
|
|
#define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK)
|
|
#define SMC_STOPCTRL_PSTOPO_MASK (0xC0U)
|
|
#define SMC_STOPCTRL_PSTOPO_SHIFT (6U)
|
|
#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK)
|
|
|
|
/*! @name PMSTAT - Power Mode Status register */
|
|
#define SMC_PMSTAT_PMSTAT_MASK (0x7FU)
|
|
#define SMC_PMSTAT_PMSTAT_SHIFT (0U)
|
|
#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group SMC_Register_Masks */
|
|
|
|
/* SMC - Peripheral instance base addresses */
|
|
/** Peripheral SMC base address */
|
|
#define SMC_BASE (0x4007E000u)
|
|
/** Peripheral SMC base pointer */
|
|
#define SMC ((SMC_Type *)SMC_BASE)
|
|
/** Array initializer of SMC peripheral base addresses */
|
|
#define SMC_BASE_ADDRS \
|
|
{ SMC_BASE }
|
|
/** Array initializer of SMC peripheral base pointers */
|
|
#define SMC_BASE_PTRS \
|
|
{ SMC }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group SMC_Peripheral_Access_Layer */
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- SPI Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** SPI - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint8_t C1; /**< SPI control register 1, offset: 0x0 */
|
|
__IO uint8_t C2; /**< SPI control register 2, offset: 0x1 */
|
|
__IO uint8_t BR; /**< SPI baud rate register, offset: 0x2 */
|
|
__IO uint8_t S; /**< SPI status register, offset: 0x3 */
|
|
uint8_t RESERVED_0[1];
|
|
__IO uint8_t D; /**< SPI data register, offset: 0x5 */
|
|
uint8_t RESERVED_1[1];
|
|
__IO uint8_t M; /**< SPI match register, offset: 0x7 */
|
|
} SPI_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- SPI Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup SPI_Register_Masks SPI Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name C1 - SPI control register 1 */
|
|
#define SPI_C1_LSBFE_MASK (0x1U)
|
|
#define SPI_C1_LSBFE_SHIFT (0U)
|
|
#define SPI_C1_LSBFE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_LSBFE_SHIFT)) & SPI_C1_LSBFE_MASK)
|
|
#define SPI_C1_SSOE_MASK (0x2U)
|
|
#define SPI_C1_SSOE_SHIFT (1U)
|
|
#define SPI_C1_SSOE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SSOE_SHIFT)) & SPI_C1_SSOE_MASK)
|
|
#define SPI_C1_CPHA_MASK (0x4U)
|
|
#define SPI_C1_CPHA_SHIFT (2U)
|
|
#define SPI_C1_CPHA(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPHA_SHIFT)) & SPI_C1_CPHA_MASK)
|
|
#define SPI_C1_CPOL_MASK (0x8U)
|
|
#define SPI_C1_CPOL_SHIFT (3U)
|
|
#define SPI_C1_CPOL(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPOL_SHIFT)) & SPI_C1_CPOL_MASK)
|
|
#define SPI_C1_MSTR_MASK (0x10U)
|
|
#define SPI_C1_MSTR_SHIFT (4U)
|
|
#define SPI_C1_MSTR(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_MSTR_SHIFT)) & SPI_C1_MSTR_MASK)
|
|
#define SPI_C1_SPTIE_MASK (0x20U)
|
|
#define SPI_C1_SPTIE_SHIFT (5U)
|
|
#define SPI_C1_SPTIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPTIE_SHIFT)) & SPI_C1_SPTIE_MASK)
|
|
#define SPI_C1_SPE_MASK (0x40U)
|
|
#define SPI_C1_SPE_SHIFT (6U)
|
|
#define SPI_C1_SPE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPE_SHIFT)) & SPI_C1_SPE_MASK)
|
|
#define SPI_C1_SPIE_MASK (0x80U)
|
|
#define SPI_C1_SPIE_SHIFT (7U)
|
|
#define SPI_C1_SPIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPIE_SHIFT)) & SPI_C1_SPIE_MASK)
|
|
|
|
/*! @name C2 - SPI control register 2 */
|
|
#define SPI_C2_SPC0_MASK (0x1U)
|
|
#define SPI_C2_SPC0_SHIFT (0U)
|
|
#define SPI_C2_SPC0(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPC0_SHIFT)) & SPI_C2_SPC0_MASK)
|
|
#define SPI_C2_SPISWAI_MASK (0x2U)
|
|
#define SPI_C2_SPISWAI_SHIFT (1U)
|
|
#define SPI_C2_SPISWAI(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPISWAI_SHIFT)) & SPI_C2_SPISWAI_MASK)
|
|
#define SPI_C2_RXDMAE_MASK (0x4U)
|
|
#define SPI_C2_RXDMAE_SHIFT (2U)
|
|
#define SPI_C2_RXDMAE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_RXDMAE_SHIFT)) & SPI_C2_RXDMAE_MASK)
|
|
#define SPI_C2_BIDIROE_MASK (0x8U)
|
|
#define SPI_C2_BIDIROE_SHIFT (3U)
|
|
#define SPI_C2_BIDIROE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_BIDIROE_SHIFT)) & SPI_C2_BIDIROE_MASK)
|
|
#define SPI_C2_MODFEN_MASK (0x10U)
|
|
#define SPI_C2_MODFEN_SHIFT (4U)
|
|
#define SPI_C2_MODFEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_MODFEN_SHIFT)) & SPI_C2_MODFEN_MASK)
|
|
#define SPI_C2_TXDMAE_MASK (0x20U)
|
|
#define SPI_C2_TXDMAE_SHIFT (5U)
|
|
#define SPI_C2_TXDMAE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_TXDMAE_SHIFT)) & SPI_C2_TXDMAE_MASK)
|
|
#define SPI_C2_SPMIE_MASK (0x80U)
|
|
#define SPI_C2_SPMIE_SHIFT (7U)
|
|
#define SPI_C2_SPMIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPMIE_SHIFT)) & SPI_C2_SPMIE_MASK)
|
|
|
|
/*! @name BR - SPI baud rate register */
|
|
#define SPI_BR_SPR_MASK (0xFU)
|
|
#define SPI_BR_SPR_SHIFT (0U)
|
|
#define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPR_SHIFT)) & SPI_BR_SPR_MASK)
|
|
#define SPI_BR_SPPR_MASK (0x70U)
|
|
#define SPI_BR_SPPR_SHIFT (4U)
|
|
#define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPPR_SHIFT)) & SPI_BR_SPPR_MASK)
|
|
|
|
/*! @name S - SPI status register */
|
|
#define SPI_S_MODF_MASK (0x10U)
|
|
#define SPI_S_MODF_SHIFT (4U)
|
|
#define SPI_S_MODF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_MODF_SHIFT)) & SPI_S_MODF_MASK)
|
|
#define SPI_S_SPTEF_MASK (0x20U)
|
|
#define SPI_S_SPTEF_SHIFT (5U)
|
|
#define SPI_S_SPTEF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPTEF_SHIFT)) & SPI_S_SPTEF_MASK)
|
|
#define SPI_S_SPMF_MASK (0x40U)
|
|
#define SPI_S_SPMF_SHIFT (6U)
|
|
#define SPI_S_SPMF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPMF_SHIFT)) & SPI_S_SPMF_MASK)
|
|
#define SPI_S_SPRF_MASK (0x80U)
|
|
#define SPI_S_SPRF_SHIFT (7U)
|
|
#define SPI_S_SPRF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPRF_SHIFT)) & SPI_S_SPRF_MASK)
|
|
|
|
/*! @name D - SPI data register */
|
|
#define SPI_D_Bits_MASK (0xFFU)
|
|
#define SPI_D_Bits_SHIFT (0U)
|
|
#define SPI_D_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_D_Bits_SHIFT)) & SPI_D_Bits_MASK)
|
|
|
|
/*! @name M - SPI match register */
|
|
#define SPI_M_Bits_MASK (0xFFU)
|
|
#define SPI_M_Bits_SHIFT (0U)
|
|
#define SPI_M_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_M_Bits_SHIFT)) & SPI_M_Bits_MASK)
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group SPI_Register_Masks */
|
|
|
|
/* SPI - Peripheral instance base addresses */
|
|
/** Peripheral SPI0 base address */
|
|
#define SPI0_BASE (0x40076000u)
|
|
/** Peripheral SPI0 base pointer */
|
|
#define SPI0 ((SPI_Type *)SPI0_BASE)
|
|
/** Peripheral SPI1 base address */
|
|
#define SPI1_BASE (0x40077000u)
|
|
/** Peripheral SPI1 base pointer */
|
|
#define SPI1 ((SPI_Type *)SPI1_BASE)
|
|
/** Array initializer of SPI peripheral base addresses */
|
|
#define SPI_BASE_ADDRS \
|
|
{ SPI0_BASE, SPI1_BASE }
|
|
/** Array initializer of SPI peripheral base pointers */
|
|
#define SPI_BASE_PTRS \
|
|
{ SPI0, SPI1 }
|
|
/** Interrupt vectors for the SPI peripheral type */
|
|
#define SPI_IRQS \
|
|
{ SPI0_IRQn, SPI1_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group SPI_Peripheral_Access_Layer */
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- TPM Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** TPM - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t SC; /**< Status and Control, offset: 0x0 */
|
|
__IO uint32_t CNT; /**< Counter, offset: 0x4 */
|
|
__IO uint32_t MOD; /**< Modulo, offset: 0x8 */
|
|
struct { /* offset: 0xC, array step: 0x8 */
|
|
__IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
|
|
__IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
|
|
} CONTROLS[6];
|
|
uint8_t RESERVED_0[20];
|
|
__IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
|
|
uint8_t RESERVED_1[48];
|
|
__IO uint32_t CONF; /**< Configuration, offset: 0x84 */
|
|
} TPM_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- TPM Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup TPM_Register_Masks TPM Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name SC - Status and Control */
|
|
#define TPM_SC_PS_MASK (0x7U)
|
|
#define TPM_SC_PS_SHIFT (0U)
|
|
#define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)
|
|
#define TPM_SC_CMOD_MASK (0x18U)
|
|
#define TPM_SC_CMOD_SHIFT (3U)
|
|
#define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)
|
|
#define TPM_SC_CPWMS_MASK (0x20U)
|
|
#define TPM_SC_CPWMS_SHIFT (5U)
|
|
#define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)
|
|
#define TPM_SC_TOIE_MASK (0x40U)
|
|
#define TPM_SC_TOIE_SHIFT (6U)
|
|
#define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)
|
|
#define TPM_SC_TOF_MASK (0x80U)
|
|
#define TPM_SC_TOF_SHIFT (7U)
|
|
#define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)
|
|
#define TPM_SC_DMA_MASK (0x100U)
|
|
#define TPM_SC_DMA_SHIFT (8U)
|
|
#define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK)
|
|
|
|
/*! @name CNT - Counter */
|
|
#define TPM_CNT_COUNT_MASK (0xFFFFU)
|
|
#define TPM_CNT_COUNT_SHIFT (0U)
|
|
#define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK)
|
|
|
|
/*! @name MOD - Modulo */
|
|
#define TPM_MOD_MOD_MASK (0xFFFFU)
|
|
#define TPM_MOD_MOD_SHIFT (0U)
|
|
#define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK)
|
|
|
|
/*! @name CnSC - Channel (n) Status and Control */
|
|
#define TPM_CnSC_DMA_MASK (0x1U)
|
|
#define TPM_CnSC_DMA_SHIFT (0U)
|
|
#define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK)
|
|
#define TPM_CnSC_ELSA_MASK (0x4U)
|
|
#define TPM_CnSC_ELSA_SHIFT (2U)
|
|
#define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK)
|
|
#define TPM_CnSC_ELSB_MASK (0x8U)
|
|
#define TPM_CnSC_ELSB_SHIFT (3U)
|
|
#define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK)
|
|
#define TPM_CnSC_MSA_MASK (0x10U)
|
|
#define TPM_CnSC_MSA_SHIFT (4U)
|
|
#define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK)
|
|
#define TPM_CnSC_MSB_MASK (0x20U)
|
|
#define TPM_CnSC_MSB_SHIFT (5U)
|
|
#define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK)
|
|
#define TPM_CnSC_CHIE_MASK (0x40U)
|
|
#define TPM_CnSC_CHIE_SHIFT (6U)
|
|
#define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)
|
|
#define TPM_CnSC_CHF_MASK (0x80U)
|
|
#define TPM_CnSC_CHF_SHIFT (7U)
|
|
#define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)
|
|
|
|
/* The count of TPM_CnSC */
|
|
#define TPM_CnSC_COUNT (6U)
|
|
|
|
/*! @name CnV - Channel (n) Value */
|
|
#define TPM_CnV_VAL_MASK (0xFFFFU)
|
|
#define TPM_CnV_VAL_SHIFT (0U)
|
|
#define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK)
|
|
|
|
/* The count of TPM_CnV */
|
|
#define TPM_CnV_COUNT (6U)
|
|
|
|
/*! @name STATUS - Capture and Compare Status */
|
|
#define TPM_STATUS_CH0F_MASK (0x1U)
|
|
#define TPM_STATUS_CH0F_SHIFT (0U)
|
|
#define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)
|
|
#define TPM_STATUS_CH1F_MASK (0x2U)
|
|
#define TPM_STATUS_CH1F_SHIFT (1U)
|
|
#define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)
|
|
#define TPM_STATUS_CH2F_MASK (0x4U)
|
|
#define TPM_STATUS_CH2F_SHIFT (2U)
|
|
#define TPM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH2F_SHIFT)) & TPM_STATUS_CH2F_MASK)
|
|
#define TPM_STATUS_CH3F_MASK (0x8U)
|
|
#define TPM_STATUS_CH3F_SHIFT (3U)
|
|
#define TPM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH3F_SHIFT)) & TPM_STATUS_CH3F_MASK)
|
|
#define TPM_STATUS_CH4F_MASK (0x10U)
|
|
#define TPM_STATUS_CH4F_SHIFT (4U)
|
|
#define TPM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH4F_SHIFT)) & TPM_STATUS_CH4F_MASK)
|
|
#define TPM_STATUS_CH5F_MASK (0x20U)
|
|
#define TPM_STATUS_CH5F_SHIFT (5U)
|
|
#define TPM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH5F_SHIFT)) & TPM_STATUS_CH5F_MASK)
|
|
#define TPM_STATUS_TOF_MASK (0x100U)
|
|
#define TPM_STATUS_TOF_SHIFT (8U)
|
|
#define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)
|
|
|
|
/*! @name CONF - Configuration */
|
|
#define TPM_CONF_DOZEEN_MASK (0x20U)
|
|
#define TPM_CONF_DOZEEN_SHIFT (5U)
|
|
#define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)
|
|
#define TPM_CONF_DBGMODE_MASK (0xC0U)
|
|
#define TPM_CONF_DBGMODE_SHIFT (6U)
|
|
#define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)
|
|
#define TPM_CONF_GTBEEN_MASK (0x200U)
|
|
#define TPM_CONF_GTBEEN_SHIFT (9U)
|
|
#define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)
|
|
#define TPM_CONF_CSOT_MASK (0x10000U)
|
|
#define TPM_CONF_CSOT_SHIFT (16U)
|
|
#define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)
|
|
#define TPM_CONF_CSOO_MASK (0x20000U)
|
|
#define TPM_CONF_CSOO_SHIFT (17U)
|
|
#define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)
|
|
#define TPM_CONF_CROT_MASK (0x40000U)
|
|
#define TPM_CONF_CROT_SHIFT (18U)
|
|
#define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)
|
|
#define TPM_CONF_TRGSEL_MASK (0xF000000U)
|
|
#define TPM_CONF_TRGSEL_SHIFT (24U)
|
|
#define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group TPM_Register_Masks */
|
|
|
|
/* TPM - Peripheral instance base addresses */
|
|
/** Peripheral TPM0 base address */
|
|
#define TPM0_BASE (0x40038000u)
|
|
/** Peripheral TPM0 base pointer */
|
|
#define TPM0 ((TPM_Type *)TPM0_BASE)
|
|
/** Peripheral TPM1 base address */
|
|
#define TPM1_BASE (0x40039000u)
|
|
/** Peripheral TPM1 base pointer */
|
|
#define TPM1 ((TPM_Type *)TPM1_BASE)
|
|
/** Peripheral TPM2 base address */
|
|
#define TPM2_BASE (0x4003A000u)
|
|
/** Peripheral TPM2 base pointer */
|
|
#define TPM2 ((TPM_Type *)TPM2_BASE)
|
|
/** Array initializer of TPM peripheral base addresses */
|
|
#define TPM_BASE_ADDRS \
|
|
{ TPM0_BASE, TPM1_BASE, TPM2_BASE }
|
|
/** Array initializer of TPM peripheral base pointers */
|
|
#define TPM_BASE_PTRS \
|
|
{ TPM0, TPM1, TPM2 }
|
|
/** Interrupt vectors for the TPM peripheral type */
|
|
#define TPM_IRQS \
|
|
{ TPM0_IRQn, TPM1_IRQn, TPM2_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group TPM_Peripheral_Access_Layer */
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- TSI Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** TSI - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
|
|
__IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
|
|
__IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
|
|
} TSI_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- TSI Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup TSI_Register_Masks TSI Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name GENCS - TSI General Control and Status Register */
|
|
#define TSI_GENCS_CURSW_MASK (0x2U)
|
|
#define TSI_GENCS_CURSW_SHIFT (1U)
|
|
#define TSI_GENCS_CURSW(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_CURSW_SHIFT)) & TSI_GENCS_CURSW_MASK)
|
|
#define TSI_GENCS_EOSF_MASK (0x4U)
|
|
#define TSI_GENCS_EOSF_SHIFT (2U)
|
|
#define TSI_GENCS_EOSF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK)
|
|
#define TSI_GENCS_SCNIP_MASK (0x8U)
|
|
#define TSI_GENCS_SCNIP_SHIFT (3U)
|
|
#define TSI_GENCS_SCNIP(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK)
|
|
#define TSI_GENCS_STM_MASK (0x10U)
|
|
#define TSI_GENCS_STM_SHIFT (4U)
|
|
#define TSI_GENCS_STM(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK)
|
|
#define TSI_GENCS_STPE_MASK (0x20U)
|
|
#define TSI_GENCS_STPE_SHIFT (5U)
|
|
#define TSI_GENCS_STPE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK)
|
|
#define TSI_GENCS_TSIIEN_MASK (0x40U)
|
|
#define TSI_GENCS_TSIIEN_SHIFT (6U)
|
|
#define TSI_GENCS_TSIIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIEN_SHIFT)) & TSI_GENCS_TSIIEN_MASK)
|
|
#define TSI_GENCS_TSIEN_MASK (0x80U)
|
|
#define TSI_GENCS_TSIEN_SHIFT (7U)
|
|
#define TSI_GENCS_TSIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK)
|
|
#define TSI_GENCS_NSCN_MASK (0x1F00U)
|
|
#define TSI_GENCS_NSCN_SHIFT (8U)
|
|
#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK)
|
|
#define TSI_GENCS_PS_MASK (0xE000U)
|
|
#define TSI_GENCS_PS_SHIFT (13U)
|
|
#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK)
|
|
#define TSI_GENCS_EXTCHRG_MASK (0x70000U)
|
|
#define TSI_GENCS_EXTCHRG_SHIFT (16U)
|
|
#define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTCHRG_SHIFT)) & TSI_GENCS_EXTCHRG_MASK)
|
|
#define TSI_GENCS_DVOLT_MASK (0x180000U)
|
|
#define TSI_GENCS_DVOLT_SHIFT (19U)
|
|
#define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DVOLT_SHIFT)) & TSI_GENCS_DVOLT_MASK)
|
|
#define TSI_GENCS_REFCHRG_MASK (0xE00000U)
|
|
#define TSI_GENCS_REFCHRG_SHIFT (21U)
|
|
#define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_REFCHRG_SHIFT)) & TSI_GENCS_REFCHRG_MASK)
|
|
#define TSI_GENCS_MODE_MASK (0xF000000U)
|
|
#define TSI_GENCS_MODE_SHIFT (24U)
|
|
#define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_MODE_SHIFT)) & TSI_GENCS_MODE_MASK)
|
|
#define TSI_GENCS_ESOR_MASK (0x10000000U)
|
|
#define TSI_GENCS_ESOR_SHIFT (28U)
|
|
#define TSI_GENCS_ESOR(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK)
|
|
#define TSI_GENCS_OUTRGF_MASK (0x80000000U)
|
|
#define TSI_GENCS_OUTRGF_SHIFT (31U)
|
|
#define TSI_GENCS_OUTRGF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK)
|
|
|
|
/*! @name DATA - TSI DATA Register */
|
|
#define TSI_DATA_TSICNT_MASK (0xFFFFU)
|
|
#define TSI_DATA_TSICNT_SHIFT (0U)
|
|
#define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICNT_SHIFT)) & TSI_DATA_TSICNT_MASK)
|
|
#define TSI_DATA_SWTS_MASK (0x400000U)
|
|
#define TSI_DATA_SWTS_SHIFT (22U)
|
|
#define TSI_DATA_SWTS(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_SWTS_SHIFT)) & TSI_DATA_SWTS_MASK)
|
|
#define TSI_DATA_DMAEN_MASK (0x800000U)
|
|
#define TSI_DATA_DMAEN_SHIFT (23U)
|
|
#define TSI_DATA_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_DMAEN_SHIFT)) & TSI_DATA_DMAEN_MASK)
|
|
#define TSI_DATA_TSICH_MASK (0xF0000000U)
|
|
#define TSI_DATA_TSICH_SHIFT (28U)
|
|
#define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICH_SHIFT)) & TSI_DATA_TSICH_MASK)
|
|
|
|
/*! @name TSHD - TSI Threshold Register */
|
|
#define TSI_TSHD_THRESL_MASK (0xFFFFU)
|
|
#define TSI_TSHD_THRESL_SHIFT (0U)
|
|
#define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESL_SHIFT)) & TSI_TSHD_THRESL_MASK)
|
|
#define TSI_TSHD_THRESH_MASK (0xFFFF0000U)
|
|
#define TSI_TSHD_THRESH_SHIFT (16U)
|
|
#define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESH_SHIFT)) & TSI_TSHD_THRESH_MASK)
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group TSI_Register_Masks */
|
|
|
|
/* TSI - Peripheral instance base addresses */
|
|
/** Peripheral TSI0 base address */
|
|
#define TSI0_BASE (0x40045000u)
|
|
/** Peripheral TSI0 base pointer */
|
|
#define TSI0 ((TSI_Type *)TSI0_BASE)
|
|
/** Array initializer of TSI peripheral base addresses */
|
|
#define TSI_BASE_ADDRS \
|
|
{ TSI0_BASE }
|
|
/** Array initializer of TSI peripheral base pointers */
|
|
#define TSI_BASE_PTRS \
|
|
{ TSI0 }
|
|
/** Interrupt vectors for the TSI peripheral type */
|
|
#define TSI_IRQS \
|
|
{ TSI0_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group TSI_Peripheral_Access_Layer */
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- UART Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** UART - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint8_t BDH; /**< UART Baud Rate Register: High, offset: 0x0 */
|
|
__IO uint8_t BDL; /**< UART Baud Rate Register: Low, offset: 0x1 */
|
|
__IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
|
|
__IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
|
|
__I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
|
|
__IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
|
|
__IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
|
|
__IO uint8_t D; /**< UART Data Register, offset: 0x7 */
|
|
__IO uint8_t C4; /**< UART Control Register 4, offset: 0x8 */
|
|
} UART_Type;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- UART Register Masks
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup UART_Register_Masks UART Register Masks
|
|
* @{
|
|
*/
|
|
|
|
/*! @name BDH - UART Baud Rate Register: High */
|
|
#define UART_BDH_SBR_MASK (0x1FU)
|
|
#define UART_BDH_SBR_SHIFT (0U)
|
|
#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK)
|
|
#define UART_BDH_SBNS_MASK (0x20U)
|
|
#define UART_BDH_SBNS_SHIFT (5U)
|
|
#define UART_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBNS_SHIFT)) & UART_BDH_SBNS_MASK)
|
|
#define UART_BDH_RXEDGIE_MASK (0x40U)
|
|
#define UART_BDH_RXEDGIE_SHIFT (6U)
|
|
#define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK)
|
|
#define UART_BDH_LBKDIE_MASK (0x80U)
|
|
#define UART_BDH_LBKDIE_SHIFT (7U)
|
|
#define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK)
|
|
|
|
/*! @name BDL - UART Baud Rate Register: Low */
|
|
#define UART_BDL_SBR_MASK (0xFFU)
|
|
#define UART_BDL_SBR_SHIFT (0U)
|
|
#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK)
|
|
|
|
/*! @name C1 - UART Control Register 1 */
|
|
#define UART_C1_PT_MASK (0x1U)
|
|
#define UART_C1_PT_SHIFT (0U)
|
|
#define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK)
|
|
#define UART_C1_PE_MASK (0x2U)
|
|
#define UART_C1_PE_SHIFT (1U)
|
|
#define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK)
|
|
#define UART_C1_ILT_MASK (0x4U)
|
|
#define UART_C1_ILT_SHIFT (2U)
|
|
#define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK)
|
|
#define UART_C1_WAKE_MASK (0x8U)
|
|
#define UART_C1_WAKE_SHIFT (3U)
|
|
#define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK)
|
|
#define UART_C1_M_MASK (0x10U)
|
|
#define UART_C1_M_SHIFT (4U)
|
|
#define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK)
|
|
#define UART_C1_RSRC_MASK (0x20U)
|
|
#define UART_C1_RSRC_SHIFT (5U)
|
|
#define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK)
|
|
#define UART_C1_UARTSWAI_MASK (0x40U)
|
|
#define UART_C1_UARTSWAI_SHIFT (6U)
|
|
#define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK)
|
|
#define UART_C1_LOOPS_MASK (0x80U)
|
|
#define UART_C1_LOOPS_SHIFT (7U)
|
|
#define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK)
|
|
|
|
/*! @name C2 - UART Control Register 2 */
|
|
#define UART_C2_SBK_MASK (0x1U)
|
|
#define UART_C2_SBK_SHIFT (0U)
|
|
#define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK)
|
|
#define UART_C2_RWU_MASK (0x2U)
|
|
#define UART_C2_RWU_SHIFT (1U)
|
|
#define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK)
|
|
#define UART_C2_RE_MASK (0x4U)
|
|
#define UART_C2_RE_SHIFT (2U)
|
|
#define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK)
|
|
#define UART_C2_TE_MASK (0x8U)
|
|
#define UART_C2_TE_SHIFT (3U)
|
|
#define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK)
|
|
#define UART_C2_ILIE_MASK (0x10U)
|
|
#define UART_C2_ILIE_SHIFT (4U)
|
|
#define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK)
|
|
#define UART_C2_RIE_MASK (0x20U)
|
|
#define UART_C2_RIE_SHIFT (5U)
|
|
#define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK)
|
|
#define UART_C2_TCIE_MASK (0x40U)
|
|
#define UART_C2_TCIE_SHIFT (6U)
|
|
#define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK)
|
|
#define UART_C2_TIE_MASK (0x80U)
|
|
#define UART_C2_TIE_SHIFT (7U)
|
|
#define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK)
|
|
|
|
/*! @name S1 - UART Status Register 1 */
|
|
#define UART_S1_PF_MASK (0x1U)
|
|
#define UART_S1_PF_SHIFT (0U)
|
|
#define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK)
|
|
#define UART_S1_FE_MASK (0x2U)
|
|
#define UART_S1_FE_SHIFT (1U)
|
|
#define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK)
|
|
#define UART_S1_NF_MASK (0x4U)
|
|
#define UART_S1_NF_SHIFT (2U)
|
|
#define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK)
|
|
#define UART_S1_OR_MASK (0x8U)
|
|
#define UART_S1_OR_SHIFT (3U)
|
|
#define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK)
|
|
#define UART_S1_IDLE_MASK (0x10U)
|
|
#define UART_S1_IDLE_SHIFT (4U)
|
|
#define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK)
|
|
#define UART_S1_RDRF_MASK (0x20U)
|
|
#define UART_S1_RDRF_SHIFT (5U)
|
|
#define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK)
|
|
#define UART_S1_TC_MASK (0x40U)
|
|
#define UART_S1_TC_SHIFT (6U)
|
|
#define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK)
|
|
#define UART_S1_TDRE_MASK (0x80U)
|
|
#define UART_S1_TDRE_SHIFT (7U)
|
|
#define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK)
|
|
|
|
/*! @name S2 - UART Status Register 2 */
|
|
#define UART_S2_RAF_MASK (0x1U)
|
|
#define UART_S2_RAF_SHIFT (0U)
|
|
#define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK)
|
|
#define UART_S2_LBKDE_MASK (0x2U)
|
|
#define UART_S2_LBKDE_SHIFT (1U)
|
|
#define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK)
|
|
#define UART_S2_BRK13_MASK (0x4U)
|
|
#define UART_S2_BRK13_SHIFT (2U)
|
|
#define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK)
|
|
#define UART_S2_RWUID_MASK (0x8U)
|
|
#define UART_S2_RWUID_SHIFT (3U)
|
|
#define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK)
|
|
#define UART_S2_RXINV_MASK (0x10U)
|
|
#define UART_S2_RXINV_SHIFT (4U)
|
|
#define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK)
|
|
#define UART_S2_RXEDGIF_MASK (0x40U)
|
|
#define UART_S2_RXEDGIF_SHIFT (6U)
|
|
#define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK)
|
|
#define UART_S2_LBKDIF_MASK (0x80U)
|
|
#define UART_S2_LBKDIF_SHIFT (7U)
|
|
#define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK)
|
|
|
|
/*! @name C3 - UART Control Register 3 */
|
|
#define UART_C3_PEIE_MASK (0x1U)
|
|
#define UART_C3_PEIE_SHIFT (0U)
|
|
#define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK)
|
|
#define UART_C3_FEIE_MASK (0x2U)
|
|
#define UART_C3_FEIE_SHIFT (1U)
|
|
#define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK)
|
|
#define UART_C3_NEIE_MASK (0x4U)
|
|
#define UART_C3_NEIE_SHIFT (2U)
|
|
#define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK)
|
|
#define UART_C3_ORIE_MASK (0x8U)
|
|
#define UART_C3_ORIE_SHIFT (3U)
|
|
#define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK)
|
|
#define UART_C3_TXINV_MASK (0x10U)
|
|
#define UART_C3_TXINV_SHIFT (4U)
|
|
#define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK)
|
|
#define UART_C3_TXDIR_MASK (0x20U)
|
|
#define UART_C3_TXDIR_SHIFT (5U)
|
|
#define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK)
|
|
#define UART_C3_T8_MASK (0x40U)
|
|
#define UART_C3_T8_SHIFT (6U)
|
|
#define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK)
|
|
#define UART_C3_R8_MASK (0x80U)
|
|
#define UART_C3_R8_SHIFT (7U)
|
|
#define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK)
|
|
|
|
/*! @name D - UART Data Register */
|
|
#define UART_D_R0T0_MASK (0x1U)
|
|
#define UART_D_R0T0_SHIFT (0U)
|
|
#define UART_D_R0T0(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R0T0_SHIFT)) & UART_D_R0T0_MASK)
|
|
#define UART_D_R1T1_MASK (0x2U)
|
|
#define UART_D_R1T1_SHIFT (1U)
|
|
#define UART_D_R1T1(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R1T1_SHIFT)) & UART_D_R1T1_MASK)
|
|
#define UART_D_R2T2_MASK (0x4U)
|
|
#define UART_D_R2T2_SHIFT (2U)
|
|
#define UART_D_R2T2(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R2T2_SHIFT)) & UART_D_R2T2_MASK)
|
|
#define UART_D_R3T3_MASK (0x8U)
|
|
#define UART_D_R3T3_SHIFT (3U)
|
|
#define UART_D_R3T3(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R3T3_SHIFT)) & UART_D_R3T3_MASK)
|
|
#define UART_D_R4T4_MASK (0x10U)
|
|
#define UART_D_R4T4_SHIFT (4U)
|
|
#define UART_D_R4T4(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R4T4_SHIFT)) & UART_D_R4T4_MASK)
|
|
#define UART_D_R5T5_MASK (0x20U)
|
|
#define UART_D_R5T5_SHIFT (5U)
|
|
#define UART_D_R5T5(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R5T5_SHIFT)) & UART_D_R5T5_MASK)
|
|
#define UART_D_R6T6_MASK (0x40U)
|
|
#define UART_D_R6T6_SHIFT (6U)
|
|
#define UART_D_R6T6(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R6T6_SHIFT)) & UART_D_R6T6_MASK)
|
|
#define UART_D_R7T7_MASK (0x80U)
|
|
#define UART_D_R7T7_SHIFT (7U)
|
|
#define UART_D_R7T7(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R7T7_SHIFT)) & UART_D_R7T7_MASK)
|
|
|
|
/*! @name C4 - UART Control Register 4 */
|
|
#define UART_C4_RDMAS_MASK (0x20U)
|
|
#define UART_C4_RDMAS_SHIFT (5U)
|
|
#define UART_C4_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_RDMAS_SHIFT)) & UART_C4_RDMAS_MASK)
|
|
#define UART_C4_TDMAS_MASK (0x80U)
|
|
#define UART_C4_TDMAS_SHIFT (7U)
|
|
#define UART_C4_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_TDMAS_SHIFT)) & UART_C4_TDMAS_MASK)
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group UART_Register_Masks */
|
|
|
|
/* UART - Peripheral instance base addresses */
|
|
/** Peripheral UART1 base address */
|
|
#define UART1_BASE (0x4006B000u)
|
|
/** Peripheral UART1 base pointer */
|
|
#define UART1 ((UART_Type *)UART1_BASE)
|
|
/** Peripheral UART2 base address */
|
|
#define UART2_BASE (0x4006C000u)
|
|
/** Peripheral UART2 base pointer */
|
|
#define UART2 ((UART_Type *)UART2_BASE)
|
|
/** Array initializer of UART peripheral base addresses */
|
|
#define UART_BASE_ADDRS \
|
|
{ 0u, UART1_BASE, UART2_BASE }
|
|
/** Array initializer of UART peripheral base pointers */
|
|
#define UART_BASE_PTRS \
|
|
{ (UART_Type *)0u, UART1, UART2 }
|
|
/** Interrupt vectors for the UART peripheral type */
|
|
#define UART_RX_TX_IRQS \
|
|
{ NotAvail_IRQn, UART1_IRQn, UART2_IRQn }
|
|
#define UART_ERR_IRQS \
|
|
{ NotAvail_IRQn, UART1_IRQn, UART2_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group UART_Peripheral_Access_Layer */
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- UART0 Peripheral Access Layer
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup UART0_Peripheral_Access_Layer UART0 Peripheral Access Layer
|
|
* @{
|
|
*/
|
|
|
|
/** UART0 - Register Layout Typedef */
|
|
typedef struct {
|
|
__IO uint8_t BDH; /**< UART Baud Rate Register High, offset: 0x0 */
|
|
__IO uint8_t BDL; /**< UART Baud Rate Register Low, offset: 0x1 */
|
|
__IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
|
|
__IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
|
|
__IO uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
|
|
__IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
|
|
__IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
|
|
__IO uint8_t D; /**< UART Data Register, offset: 0x7 */
|
|
__IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
|
|
__IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
|
|
__IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
|
|
__IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
|
|
} UART0_Type;
|
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/* ----------------------------------------------------------------------------
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-- UART0 Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup UART0_Register_Masks UART0 Register Masks
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* @{
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*/
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/*! @name BDH - UART Baud Rate Register High */
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#define UART0_BDH_SBR_MASK (0x1FU)
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#define UART0_BDH_SBR_SHIFT (0U)
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#define UART0_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDH_SBR_SHIFT)) & UART0_BDH_SBR_MASK)
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#define UART0_BDH_SBNS_MASK (0x20U)
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#define UART0_BDH_SBNS_SHIFT (5U)
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#define UART0_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDH_SBNS_SHIFT)) & UART0_BDH_SBNS_MASK)
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#define UART0_BDH_RXEDGIE_MASK (0x40U)
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#define UART0_BDH_RXEDGIE_SHIFT (6U)
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#define UART0_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDH_RXEDGIE_SHIFT)) & UART0_BDH_RXEDGIE_MASK)
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#define UART0_BDH_LBKDIE_MASK (0x80U)
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#define UART0_BDH_LBKDIE_SHIFT (7U)
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#define UART0_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDH_LBKDIE_SHIFT)) & UART0_BDH_LBKDIE_MASK)
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/*! @name BDL - UART Baud Rate Register Low */
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#define UART0_BDL_SBR_MASK (0xFFU)
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#define UART0_BDL_SBR_SHIFT (0U)
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#define UART0_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART0_BDL_SBR_SHIFT)) & UART0_BDL_SBR_MASK)
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/*! @name C1 - UART Control Register 1 */
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#define UART0_C1_PT_MASK (0x1U)
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#define UART0_C1_PT_SHIFT (0U)
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#define UART0_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_PT_SHIFT)) & UART0_C1_PT_MASK)
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#define UART0_C1_PE_MASK (0x2U)
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#define UART0_C1_PE_SHIFT (1U)
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#define UART0_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_PE_SHIFT)) & UART0_C1_PE_MASK)
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#define UART0_C1_ILT_MASK (0x4U)
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#define UART0_C1_ILT_SHIFT (2U)
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#define UART0_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_ILT_SHIFT)) & UART0_C1_ILT_MASK)
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#define UART0_C1_WAKE_MASK (0x8U)
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#define UART0_C1_WAKE_SHIFT (3U)
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#define UART0_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_WAKE_SHIFT)) & UART0_C1_WAKE_MASK)
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#define UART0_C1_M_MASK (0x10U)
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#define UART0_C1_M_SHIFT (4U)
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#define UART0_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_M_SHIFT)) & UART0_C1_M_MASK)
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#define UART0_C1_RSRC_MASK (0x20U)
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#define UART0_C1_RSRC_SHIFT (5U)
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#define UART0_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_RSRC_SHIFT)) & UART0_C1_RSRC_MASK)
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#define UART0_C1_DOZEEN_MASK (0x40U)
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#define UART0_C1_DOZEEN_SHIFT (6U)
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#define UART0_C1_DOZEEN(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_DOZEEN_SHIFT)) & UART0_C1_DOZEEN_MASK)
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#define UART0_C1_LOOPS_MASK (0x80U)
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#define UART0_C1_LOOPS_SHIFT (7U)
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#define UART0_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART0_C1_LOOPS_SHIFT)) & UART0_C1_LOOPS_MASK)
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/*! @name C2 - UART Control Register 2 */
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#define UART0_C2_SBK_MASK (0x1U)
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#define UART0_C2_SBK_SHIFT (0U)
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#define UART0_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_SBK_SHIFT)) & UART0_C2_SBK_MASK)
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#define UART0_C2_RWU_MASK (0x2U)
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#define UART0_C2_RWU_SHIFT (1U)
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#define UART0_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_RWU_SHIFT)) & UART0_C2_RWU_MASK)
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#define UART0_C2_RE_MASK (0x4U)
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#define UART0_C2_RE_SHIFT (2U)
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#define UART0_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_RE_SHIFT)) & UART0_C2_RE_MASK)
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#define UART0_C2_TE_MASK (0x8U)
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#define UART0_C2_TE_SHIFT (3U)
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#define UART0_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_TE_SHIFT)) & UART0_C2_TE_MASK)
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#define UART0_C2_ILIE_MASK (0x10U)
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#define UART0_C2_ILIE_SHIFT (4U)
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#define UART0_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_ILIE_SHIFT)) & UART0_C2_ILIE_MASK)
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#define UART0_C2_RIE_MASK (0x20U)
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#define UART0_C2_RIE_SHIFT (5U)
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#define UART0_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_RIE_SHIFT)) & UART0_C2_RIE_MASK)
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#define UART0_C2_TCIE_MASK (0x40U)
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#define UART0_C2_TCIE_SHIFT (6U)
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#define UART0_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_TCIE_SHIFT)) & UART0_C2_TCIE_MASK)
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#define UART0_C2_TIE_MASK (0x80U)
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#define UART0_C2_TIE_SHIFT (7U)
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#define UART0_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C2_TIE_SHIFT)) & UART0_C2_TIE_MASK)
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/*! @name S1 - UART Status Register 1 */
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#define UART0_S1_PF_MASK (0x1U)
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#define UART0_S1_PF_SHIFT (0U)
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#define UART0_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_PF_SHIFT)) & UART0_S1_PF_MASK)
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#define UART0_S1_FE_MASK (0x2U)
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#define UART0_S1_FE_SHIFT (1U)
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#define UART0_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_FE_SHIFT)) & UART0_S1_FE_MASK)
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#define UART0_S1_NF_MASK (0x4U)
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#define UART0_S1_NF_SHIFT (2U)
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#define UART0_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_NF_SHIFT)) & UART0_S1_NF_MASK)
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#define UART0_S1_OR_MASK (0x8U)
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#define UART0_S1_OR_SHIFT (3U)
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#define UART0_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_OR_SHIFT)) & UART0_S1_OR_MASK)
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#define UART0_S1_IDLE_MASK (0x10U)
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#define UART0_S1_IDLE_SHIFT (4U)
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#define UART0_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_IDLE_SHIFT)) & UART0_S1_IDLE_MASK)
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#define UART0_S1_RDRF_MASK (0x20U)
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#define UART0_S1_RDRF_SHIFT (5U)
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#define UART0_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_RDRF_SHIFT)) & UART0_S1_RDRF_MASK)
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#define UART0_S1_TC_MASK (0x40U)
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#define UART0_S1_TC_SHIFT (6U)
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#define UART0_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_TC_SHIFT)) & UART0_S1_TC_MASK)
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#define UART0_S1_TDRE_MASK (0x80U)
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#define UART0_S1_TDRE_SHIFT (7U)
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#define UART0_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART0_S1_TDRE_SHIFT)) & UART0_S1_TDRE_MASK)
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/*! @name S2 - UART Status Register 2 */
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#define UART0_S2_RAF_MASK (0x1U)
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#define UART0_S2_RAF_SHIFT (0U)
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#define UART0_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_RAF_SHIFT)) & UART0_S2_RAF_MASK)
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#define UART0_S2_LBKDE_MASK (0x2U)
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#define UART0_S2_LBKDE_SHIFT (1U)
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#define UART0_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_LBKDE_SHIFT)) & UART0_S2_LBKDE_MASK)
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#define UART0_S2_BRK13_MASK (0x4U)
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#define UART0_S2_BRK13_SHIFT (2U)
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#define UART0_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_BRK13_SHIFT)) & UART0_S2_BRK13_MASK)
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#define UART0_S2_RWUID_MASK (0x8U)
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#define UART0_S2_RWUID_SHIFT (3U)
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#define UART0_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_RWUID_SHIFT)) & UART0_S2_RWUID_MASK)
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#define UART0_S2_RXINV_MASK (0x10U)
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#define UART0_S2_RXINV_SHIFT (4U)
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#define UART0_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_RXINV_SHIFT)) & UART0_S2_RXINV_MASK)
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#define UART0_S2_MSBF_MASK (0x20U)
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#define UART0_S2_MSBF_SHIFT (5U)
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#define UART0_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_MSBF_SHIFT)) & UART0_S2_MSBF_MASK)
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#define UART0_S2_RXEDGIF_MASK (0x40U)
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#define UART0_S2_RXEDGIF_SHIFT (6U)
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#define UART0_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_RXEDGIF_SHIFT)) & UART0_S2_RXEDGIF_MASK)
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#define UART0_S2_LBKDIF_MASK (0x80U)
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#define UART0_S2_LBKDIF_SHIFT (7U)
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#define UART0_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART0_S2_LBKDIF_SHIFT)) & UART0_S2_LBKDIF_MASK)
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/*! @name C3 - UART Control Register 3 */
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#define UART0_C3_PEIE_MASK (0x1U)
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#define UART0_C3_PEIE_SHIFT (0U)
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#define UART0_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_PEIE_SHIFT)) & UART0_C3_PEIE_MASK)
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#define UART0_C3_FEIE_MASK (0x2U)
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#define UART0_C3_FEIE_SHIFT (1U)
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#define UART0_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_FEIE_SHIFT)) & UART0_C3_FEIE_MASK)
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#define UART0_C3_NEIE_MASK (0x4U)
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#define UART0_C3_NEIE_SHIFT (2U)
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#define UART0_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_NEIE_SHIFT)) & UART0_C3_NEIE_MASK)
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#define UART0_C3_ORIE_MASK (0x8U)
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#define UART0_C3_ORIE_SHIFT (3U)
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#define UART0_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_ORIE_SHIFT)) & UART0_C3_ORIE_MASK)
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#define UART0_C3_TXINV_MASK (0x10U)
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#define UART0_C3_TXINV_SHIFT (4U)
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#define UART0_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_TXINV_SHIFT)) & UART0_C3_TXINV_MASK)
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#define UART0_C3_TXDIR_MASK (0x20U)
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#define UART0_C3_TXDIR_SHIFT (5U)
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#define UART0_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_TXDIR_SHIFT)) & UART0_C3_TXDIR_MASK)
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#define UART0_C3_R9T8_MASK (0x40U)
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#define UART0_C3_R9T8_SHIFT (6U)
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#define UART0_C3_R9T8(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_R9T8_SHIFT)) & UART0_C3_R9T8_MASK)
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#define UART0_C3_R8T9_MASK (0x80U)
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#define UART0_C3_R8T9_SHIFT (7U)
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#define UART0_C3_R8T9(x) (((uint8_t)(((uint8_t)(x)) << UART0_C3_R8T9_SHIFT)) & UART0_C3_R8T9_MASK)
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/*! @name D - UART Data Register */
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#define UART0_D_R0T0_MASK (0x1U)
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#define UART0_D_R0T0_SHIFT (0U)
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#define UART0_D_R0T0(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R0T0_SHIFT)) & UART0_D_R0T0_MASK)
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#define UART0_D_R1T1_MASK (0x2U)
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#define UART0_D_R1T1_SHIFT (1U)
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#define UART0_D_R1T1(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R1T1_SHIFT)) & UART0_D_R1T1_MASK)
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#define UART0_D_R2T2_MASK (0x4U)
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#define UART0_D_R2T2_SHIFT (2U)
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#define UART0_D_R2T2(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R2T2_SHIFT)) & UART0_D_R2T2_MASK)
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#define UART0_D_R3T3_MASK (0x8U)
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#define UART0_D_R3T3_SHIFT (3U)
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#define UART0_D_R3T3(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R3T3_SHIFT)) & UART0_D_R3T3_MASK)
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#define UART0_D_R4T4_MASK (0x10U)
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#define UART0_D_R4T4_SHIFT (4U)
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#define UART0_D_R4T4(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R4T4_SHIFT)) & UART0_D_R4T4_MASK)
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#define UART0_D_R5T5_MASK (0x20U)
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#define UART0_D_R5T5_SHIFT (5U)
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#define UART0_D_R5T5(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R5T5_SHIFT)) & UART0_D_R5T5_MASK)
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#define UART0_D_R6T6_MASK (0x40U)
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#define UART0_D_R6T6_SHIFT (6U)
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#define UART0_D_R6T6(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R6T6_SHIFT)) & UART0_D_R6T6_MASK)
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#define UART0_D_R7T7_MASK (0x80U)
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#define UART0_D_R7T7_SHIFT (7U)
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#define UART0_D_R7T7(x) (((uint8_t)(((uint8_t)(x)) << UART0_D_R7T7_SHIFT)) & UART0_D_R7T7_MASK)
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/*! @name MA1 - UART Match Address Registers 1 */
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#define UART0_MA1_MA_MASK (0xFFU)
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#define UART0_MA1_MA_SHIFT (0U)
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#define UART0_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART0_MA1_MA_SHIFT)) & UART0_MA1_MA_MASK)
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/*! @name MA2 - UART Match Address Registers 2 */
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#define UART0_MA2_MA_MASK (0xFFU)
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#define UART0_MA2_MA_SHIFT (0U)
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#define UART0_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART0_MA2_MA_SHIFT)) & UART0_MA2_MA_MASK)
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/*! @name C4 - UART Control Register 4 */
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#define UART0_C4_OSR_MASK (0x1FU)
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#define UART0_C4_OSR_SHIFT (0U)
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#define UART0_C4_OSR(x) (((uint8_t)(((uint8_t)(x)) << UART0_C4_OSR_SHIFT)) & UART0_C4_OSR_MASK)
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#define UART0_C4_M10_MASK (0x20U)
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#define UART0_C4_M10_SHIFT (5U)
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#define UART0_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART0_C4_M10_SHIFT)) & UART0_C4_M10_MASK)
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#define UART0_C4_MAEN2_MASK (0x40U)
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#define UART0_C4_MAEN2_SHIFT (6U)
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#define UART0_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART0_C4_MAEN2_SHIFT)) & UART0_C4_MAEN2_MASK)
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#define UART0_C4_MAEN1_MASK (0x80U)
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#define UART0_C4_MAEN1_SHIFT (7U)
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#define UART0_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART0_C4_MAEN1_SHIFT)) & UART0_C4_MAEN1_MASK)
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/*! @name C5 - UART Control Register 5 */
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#define UART0_C5_RESYNCDIS_MASK (0x1U)
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#define UART0_C5_RESYNCDIS_SHIFT (0U)
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#define UART0_C5_RESYNCDIS(x) (((uint8_t)(((uint8_t)(x)) << UART0_C5_RESYNCDIS_SHIFT)) & UART0_C5_RESYNCDIS_MASK)
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#define UART0_C5_BOTHEDGE_MASK (0x2U)
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#define UART0_C5_BOTHEDGE_SHIFT (1U)
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#define UART0_C5_BOTHEDGE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C5_BOTHEDGE_SHIFT)) & UART0_C5_BOTHEDGE_MASK)
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#define UART0_C5_RDMAE_MASK (0x20U)
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#define UART0_C5_RDMAE_SHIFT (5U)
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#define UART0_C5_RDMAE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C5_RDMAE_SHIFT)) & UART0_C5_RDMAE_MASK)
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#define UART0_C5_TDMAE_MASK (0x80U)
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#define UART0_C5_TDMAE_SHIFT (7U)
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#define UART0_C5_TDMAE(x) (((uint8_t)(((uint8_t)(x)) << UART0_C5_TDMAE_SHIFT)) & UART0_C5_TDMAE_MASK)
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/*!
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* @}
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*/ /* end of group UART0_Register_Masks */
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/* UART0 - Peripheral instance base addresses */
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/** Peripheral UART0 base address */
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#define UART0_BASE (0x4006A000u)
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/** Peripheral UART0 base pointer */
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#define UART0 ((UART0_Type *)UART0_BASE)
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/** Array initializer of UART0 peripheral base addresses */
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#define UART0_BASE_ADDRS \
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{ UART0_BASE }
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/** Array initializer of UART0 peripheral base pointers */
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#define UART0_BASE_PTRS \
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{ UART0 }
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/** Interrupt vectors for the UART0 peripheral type */
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#define UART0_RX_TX_IRQS \
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{ UART0_IRQn }
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#define UART0_ERR_IRQS \
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{ UART0_IRQn }
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/*!
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* @}
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*/ /* end of group UART0_Peripheral_Access_Layer */
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/* ----------------------------------------------------------------------------
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-- USB Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
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* @{
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*/
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/** USB - Register Layout Typedef */
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typedef struct {
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__I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
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uint8_t RESERVED_0[3];
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__I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
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uint8_t RESERVED_1[3];
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__I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
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uint8_t RESERVED_2[3];
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__I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
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uint8_t RESERVED_3[3];
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__IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
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uint8_t RESERVED_4[3];
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__IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
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uint8_t RESERVED_5[3];
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__IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
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uint8_t RESERVED_6[3];
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__IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
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uint8_t RESERVED_7[99];
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__IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
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uint8_t RESERVED_8[3];
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__IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
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uint8_t RESERVED_9[3];
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__IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
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uint8_t RESERVED_10[3];
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__IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
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uint8_t RESERVED_11[3];
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__I uint8_t STAT; /**< Status register, offset: 0x90 */
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uint8_t RESERVED_12[3];
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__IO uint8_t CTL; /**< Control register, offset: 0x94 */
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uint8_t RESERVED_13[3];
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__IO uint8_t ADDR; /**< Address register, offset: 0x98 */
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uint8_t RESERVED_14[3];
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__IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
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uint8_t RESERVED_15[3];
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__IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
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uint8_t RESERVED_16[3];
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__IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
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uint8_t RESERVED_17[3];
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__IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
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uint8_t RESERVED_18[3];
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__IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
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uint8_t RESERVED_19[3];
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__IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
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uint8_t RESERVED_20[3];
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__IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
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uint8_t RESERVED_21[11];
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struct { /* offset: 0xC0, array step: 0x4 */
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__IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
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uint8_t RESERVED_0[3];
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} ENDPOINT[16];
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__IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
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uint8_t RESERVED_22[3];
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__I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
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uint8_t RESERVED_23[3];
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__IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
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uint8_t RESERVED_24[3];
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__IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
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uint8_t RESERVED_25[7];
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__IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
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} USB_Type;
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/* ----------------------------------------------------------------------------
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-- USB Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup USB_Register_Masks USB Register Masks
|
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* @{
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*/
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/*! @name PERID - Peripheral ID register */
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#define USB_PERID_ID_MASK (0x3FU)
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#define USB_PERID_ID_SHIFT (0U)
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#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
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/*! @name IDCOMP - Peripheral ID Complement register */
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#define USB_IDCOMP_NID_MASK (0x3FU)
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#define USB_IDCOMP_NID_SHIFT (0U)
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#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
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/*! @name REV - Peripheral Revision register */
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#define USB_REV_REV_MASK (0xFFU)
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#define USB_REV_REV_SHIFT (0U)
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#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
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/*! @name ADDINFO - Peripheral Additional Info register */
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#define USB_ADDINFO_IEHOST_MASK (0x1U)
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#define USB_ADDINFO_IEHOST_SHIFT (0U)
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#define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
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#define USB_ADDINFO_IRQNUM_MASK (0xF8U)
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#define USB_ADDINFO_IRQNUM_SHIFT (3U)
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#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IRQNUM_SHIFT)) & USB_ADDINFO_IRQNUM_MASK)
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/*! @name OTGISTAT - OTG Interrupt Status register */
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#define USB_OTGISTAT_AVBUSCHG_MASK (0x1U)
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#define USB_OTGISTAT_AVBUSCHG_SHIFT (0U)
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#define USB_OTGISTAT_AVBUSCHG(x) \
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(((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_AVBUSCHG_SHIFT)) & USB_OTGISTAT_AVBUSCHG_MASK)
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#define USB_OTGISTAT_B_SESS_CHG_MASK (0x4U)
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#define USB_OTGISTAT_B_SESS_CHG_SHIFT (2U)
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#define USB_OTGISTAT_B_SESS_CHG(x) \
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(((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_B_SESS_CHG_SHIFT)) & USB_OTGISTAT_B_SESS_CHG_MASK)
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#define USB_OTGISTAT_SESSVLDCHG_MASK (0x8U)
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#define USB_OTGISTAT_SESSVLDCHG_SHIFT (3U)
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#define USB_OTGISTAT_SESSVLDCHG(x) \
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(((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_SESSVLDCHG_SHIFT)) & USB_OTGISTAT_SESSVLDCHG_MASK)
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#define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U)
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#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U)
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#define USB_OTGISTAT_LINE_STATE_CHG(x) \
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(((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK)
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#define USB_OTGISTAT_ONEMSEC_MASK (0x40U)
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#define USB_OTGISTAT_ONEMSEC_SHIFT (6U)
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#define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK)
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#define USB_OTGISTAT_IDCHG_MASK (0x80U)
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#define USB_OTGISTAT_IDCHG_SHIFT (7U)
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#define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_IDCHG_SHIFT)) & USB_OTGISTAT_IDCHG_MASK)
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/*! @name OTGICR - OTG Interrupt Control Register */
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#define USB_OTGICR_AVBUSEN_MASK (0x1U)
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#define USB_OTGICR_AVBUSEN_SHIFT (0U)
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#define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_AVBUSEN_SHIFT)) & USB_OTGICR_AVBUSEN_MASK)
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#define USB_OTGICR_BSESSEN_MASK (0x4U)
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#define USB_OTGICR_BSESSEN_SHIFT (2U)
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#define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_BSESSEN_SHIFT)) & USB_OTGICR_BSESSEN_MASK)
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#define USB_OTGICR_SESSVLDEN_MASK (0x8U)
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#define USB_OTGICR_SESSVLDEN_SHIFT (3U)
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#define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_SESSVLDEN_SHIFT)) & USB_OTGICR_SESSVLDEN_MASK)
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#define USB_OTGICR_LINESTATEEN_MASK (0x20U)
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#define USB_OTGICR_LINESTATEEN_SHIFT (5U)
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#define USB_OTGICR_LINESTATEEN(x) \
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(((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK)
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#define USB_OTGICR_ONEMSECEN_MASK (0x40U)
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#define USB_OTGICR_ONEMSECEN_SHIFT (6U)
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#define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK)
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#define USB_OTGICR_IDEN_MASK (0x80U)
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#define USB_OTGICR_IDEN_SHIFT (7U)
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#define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_IDEN_SHIFT)) & USB_OTGICR_IDEN_MASK)
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/*! @name OTGSTAT - OTG Status register */
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#define USB_OTGSTAT_AVBUSVLD_MASK (0x1U)
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#define USB_OTGSTAT_AVBUSVLD_SHIFT (0U)
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#define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_AVBUSVLD_SHIFT)) & USB_OTGSTAT_AVBUSVLD_MASK)
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#define USB_OTGSTAT_BSESSEND_MASK (0x4U)
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#define USB_OTGSTAT_BSESSEND_SHIFT (2U)
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#define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_BSESSEND_SHIFT)) & USB_OTGSTAT_BSESSEND_MASK)
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#define USB_OTGSTAT_SESS_VLD_MASK (0x8U)
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#define USB_OTGSTAT_SESS_VLD_SHIFT (3U)
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#define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_SESS_VLD_SHIFT)) & USB_OTGSTAT_SESS_VLD_MASK)
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#define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U)
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#define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U)
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#define USB_OTGSTAT_LINESTATESTABLE(x) \
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(((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK)
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#define USB_OTGSTAT_ONEMSECEN_MASK (0x40U)
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#define USB_OTGSTAT_ONEMSECEN_SHIFT (6U)
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#define USB_OTGSTAT_ONEMSECEN(x) \
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(((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK)
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#define USB_OTGSTAT_ID_MASK (0x80U)
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#define USB_OTGSTAT_ID_SHIFT (7U)
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#define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ID_SHIFT)) & USB_OTGSTAT_ID_MASK)
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/*! @name OTGCTL - OTG Control register */
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#define USB_OTGCTL_OTGEN_MASK (0x4U)
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#define USB_OTGCTL_OTGEN_SHIFT (2U)
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#define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK)
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#define USB_OTGCTL_DMLOW_MASK (0x10U)
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#define USB_OTGCTL_DMLOW_SHIFT (4U)
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#define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK)
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#define USB_OTGCTL_DPLOW_MASK (0x20U)
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#define USB_OTGCTL_DPLOW_SHIFT (5U)
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#define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK)
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#define USB_OTGCTL_DPHIGH_MASK (0x80U)
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#define USB_OTGCTL_DPHIGH_SHIFT (7U)
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#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
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/*! @name ISTAT - Interrupt Status register */
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#define USB_ISTAT_USBRST_MASK (0x1U)
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#define USB_ISTAT_USBRST_SHIFT (0U)
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#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
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#define USB_ISTAT_ERROR_MASK (0x2U)
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#define USB_ISTAT_ERROR_SHIFT (1U)
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#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
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#define USB_ISTAT_SOFTOK_MASK (0x4U)
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#define USB_ISTAT_SOFTOK_SHIFT (2U)
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#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
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#define USB_ISTAT_TOKDNE_MASK (0x8U)
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#define USB_ISTAT_TOKDNE_SHIFT (3U)
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#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
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#define USB_ISTAT_SLEEP_MASK (0x10U)
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#define USB_ISTAT_SLEEP_SHIFT (4U)
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#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
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#define USB_ISTAT_RESUME_MASK (0x20U)
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#define USB_ISTAT_RESUME_SHIFT (5U)
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#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
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#define USB_ISTAT_ATTACH_MASK (0x40U)
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#define USB_ISTAT_ATTACH_SHIFT (6U)
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#define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK)
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#define USB_ISTAT_STALL_MASK (0x80U)
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#define USB_ISTAT_STALL_SHIFT (7U)
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#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
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/*! @name INTEN - Interrupt Enable register */
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#define USB_INTEN_USBRSTEN_MASK (0x1U)
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#define USB_INTEN_USBRSTEN_SHIFT (0U)
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#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
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#define USB_INTEN_ERROREN_MASK (0x2U)
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#define USB_INTEN_ERROREN_SHIFT (1U)
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#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
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#define USB_INTEN_SOFTOKEN_MASK (0x4U)
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#define USB_INTEN_SOFTOKEN_SHIFT (2U)
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#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
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#define USB_INTEN_TOKDNEEN_MASK (0x8U)
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#define USB_INTEN_TOKDNEEN_SHIFT (3U)
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#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
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#define USB_INTEN_SLEEPEN_MASK (0x10U)
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#define USB_INTEN_SLEEPEN_SHIFT (4U)
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#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
|
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#define USB_INTEN_RESUMEEN_MASK (0x20U)
|
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#define USB_INTEN_RESUMEEN_SHIFT (5U)
|
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#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
|
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#define USB_INTEN_ATTACHEN_MASK (0x40U)
|
|
#define USB_INTEN_ATTACHEN_SHIFT (6U)
|
|
#define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK)
|
|
#define USB_INTEN_STALLEN_MASK (0x80U)
|
|
#define USB_INTEN_STALLEN_SHIFT (7U)
|
|
#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
|
|
|
|
/*! @name ERRSTAT - Error Interrupt Status register */
|
|
#define USB_ERRSTAT_PIDERR_MASK (0x1U)
|
|
#define USB_ERRSTAT_PIDERR_SHIFT (0U)
|
|
#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
|
|
#define USB_ERRSTAT_CRC5EOF_MASK (0x2U)
|
|
#define USB_ERRSTAT_CRC5EOF_SHIFT (1U)
|
|
#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
|
|
#define USB_ERRSTAT_CRC16_MASK (0x4U)
|
|
#define USB_ERRSTAT_CRC16_SHIFT (2U)
|
|
#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
|
|
#define USB_ERRSTAT_DFN8_MASK (0x8U)
|
|
#define USB_ERRSTAT_DFN8_SHIFT (3U)
|
|
#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
|
|
#define USB_ERRSTAT_BTOERR_MASK (0x10U)
|
|
#define USB_ERRSTAT_BTOERR_SHIFT (4U)
|
|
#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
|
|
#define USB_ERRSTAT_DMAERR_MASK (0x20U)
|
|
#define USB_ERRSTAT_DMAERR_SHIFT (5U)
|
|
#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
|
|
#define USB_ERRSTAT_BTSERR_MASK (0x80U)
|
|
#define USB_ERRSTAT_BTSERR_SHIFT (7U)
|
|
#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
|
|
|
|
/*! @name ERREN - Error Interrupt Enable register */
|
|
#define USB_ERREN_PIDERREN_MASK (0x1U)
|
|
#define USB_ERREN_PIDERREN_SHIFT (0U)
|
|
#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
|
|
#define USB_ERREN_CRC5EOFEN_MASK (0x2U)
|
|
#define USB_ERREN_CRC5EOFEN_SHIFT (1U)
|
|
#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
|
|
#define USB_ERREN_CRC16EN_MASK (0x4U)
|
|
#define USB_ERREN_CRC16EN_SHIFT (2U)
|
|
#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
|
|
#define USB_ERREN_DFN8EN_MASK (0x8U)
|
|
#define USB_ERREN_DFN8EN_SHIFT (3U)
|
|
#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
|
|
#define USB_ERREN_BTOERREN_MASK (0x10U)
|
|
#define USB_ERREN_BTOERREN_SHIFT (4U)
|
|
#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
|
|
#define USB_ERREN_DMAERREN_MASK (0x20U)
|
|
#define USB_ERREN_DMAERREN_SHIFT (5U)
|
|
#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
|
|
#define USB_ERREN_BTSERREN_MASK (0x80U)
|
|
#define USB_ERREN_BTSERREN_SHIFT (7U)
|
|
#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
|
|
|
|
/*! @name STAT - Status register */
|
|
#define USB_STAT_ODD_MASK (0x4U)
|
|
#define USB_STAT_ODD_SHIFT (2U)
|
|
#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
|
|
#define USB_STAT_TX_MASK (0x8U)
|
|
#define USB_STAT_TX_SHIFT (3U)
|
|
#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
|
|
#define USB_STAT_ENDP_MASK (0xF0U)
|
|
#define USB_STAT_ENDP_SHIFT (4U)
|
|
#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
|
|
|
|
/*! @name CTL - Control register */
|
|
#define USB_CTL_USBENSOFEN_MASK (0x1U)
|
|
#define USB_CTL_USBENSOFEN_SHIFT (0U)
|
|
#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
|
|
#define USB_CTL_ODDRST_MASK (0x2U)
|
|
#define USB_CTL_ODDRST_SHIFT (1U)
|
|
#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
|
|
#define USB_CTL_RESUME_MASK (0x4U)
|
|
#define USB_CTL_RESUME_SHIFT (2U)
|
|
#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
|
|
#define USB_CTL_HOSTMODEEN_MASK (0x8U)
|
|
#define USB_CTL_HOSTMODEEN_SHIFT (3U)
|
|
#define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK)
|
|
#define USB_CTL_RESET_MASK (0x10U)
|
|
#define USB_CTL_RESET_SHIFT (4U)
|
|
#define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK)
|
|
#define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U)
|
|
#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U)
|
|
#define USB_CTL_TXSUSPENDTOKENBUSY(x) \
|
|
(((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
|
|
#define USB_CTL_SE0_MASK (0x40U)
|
|
#define USB_CTL_SE0_SHIFT (6U)
|
|
#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
|
|
#define USB_CTL_JSTATE_MASK (0x80U)
|
|
#define USB_CTL_JSTATE_SHIFT (7U)
|
|
#define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
|
|
|
|
/*! @name ADDR - Address register */
|
|
#define USB_ADDR_ADDR_MASK (0x7FU)
|
|
#define USB_ADDR_ADDR_SHIFT (0U)
|
|
#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
|
|
#define USB_ADDR_LSEN_MASK (0x80U)
|
|
#define USB_ADDR_LSEN_SHIFT (7U)
|
|
#define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK)
|
|
|
|
/*! @name BDTPAGE1 - BDT Page Register 1 */
|
|
#define USB_BDTPAGE1_BDTBA_MASK (0xFEU)
|
|
#define USB_BDTPAGE1_BDTBA_SHIFT (1U)
|
|
#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
|
|
|
|
/*! @name FRMNUML - Frame Number Register Low */
|
|
#define USB_FRMNUML_FRM_MASK (0xFFU)
|
|
#define USB_FRMNUML_FRM_SHIFT (0U)
|
|
#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
|
|
|
|
/*! @name FRMNUMH - Frame Number Register High */
|
|
#define USB_FRMNUMH_FRM_MASK (0x7U)
|
|
#define USB_FRMNUMH_FRM_SHIFT (0U)
|
|
#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
|
|
|
|
/*! @name TOKEN - Token register */
|
|
#define USB_TOKEN_TOKENENDPT_MASK (0xFU)
|
|
#define USB_TOKEN_TOKENENDPT_SHIFT (0U)
|
|
#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
|
|
#define USB_TOKEN_TOKENPID_MASK (0xF0U)
|
|
#define USB_TOKEN_TOKENPID_SHIFT (4U)
|
|
#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
|
|
|
|
/*! @name SOFTHLD - SOF Threshold Register */
|
|
#define USB_SOFTHLD_CNT_MASK (0xFFU)
|
|
#define USB_SOFTHLD_CNT_SHIFT (0U)
|
|
#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
|
|
|
|
/*! @name BDTPAGE2 - BDT Page Register 2 */
|
|
#define USB_BDTPAGE2_BDTBA_MASK (0xFFU)
|
|
#define USB_BDTPAGE2_BDTBA_SHIFT (0U)
|
|
#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
|
|
|
|
/*! @name BDTPAGE3 - BDT Page Register 3 */
|
|
#define USB_BDTPAGE3_BDTBA_MASK (0xFFU)
|
|
#define USB_BDTPAGE3_BDTBA_SHIFT (0U)
|
|
#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
|
|
|
|
/*! @name ENDPT - Endpoint Control register */
|
|
#define USB_ENDPT_EPHSHK_MASK (0x1U)
|
|
#define USB_ENDPT_EPHSHK_SHIFT (0U)
|
|
#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
|
|
#define USB_ENDPT_EPSTALL_MASK (0x2U)
|
|
#define USB_ENDPT_EPSTALL_SHIFT (1U)
|
|
#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
|
|
#define USB_ENDPT_EPTXEN_MASK (0x4U)
|
|
#define USB_ENDPT_EPTXEN_SHIFT (2U)
|
|
#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
|
|
#define USB_ENDPT_EPRXEN_MASK (0x8U)
|
|
#define USB_ENDPT_EPRXEN_SHIFT (3U)
|
|
#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
|
|
#define USB_ENDPT_EPCTLDIS_MASK (0x10U)
|
|
#define USB_ENDPT_EPCTLDIS_SHIFT (4U)
|
|
#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
|
|
#define USB_ENDPT_RETRYDIS_MASK (0x40U)
|
|
#define USB_ENDPT_RETRYDIS_SHIFT (6U)
|
|
#define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK)
|
|
#define USB_ENDPT_HOSTWOHUB_MASK (0x80U)
|
|
#define USB_ENDPT_HOSTWOHUB_SHIFT (7U)
|
|
#define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK)
|
|
|
|
/* The count of USB_ENDPT */
|
|
#define USB_ENDPT_COUNT (16U)
|
|
|
|
/*! @name USBCTRL - USB Control register */
|
|
#define USB_USBCTRL_PDE_MASK (0x40U)
|
|
#define USB_USBCTRL_PDE_SHIFT (6U)
|
|
#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
|
|
#define USB_USBCTRL_SUSP_MASK (0x80U)
|
|
#define USB_USBCTRL_SUSP_SHIFT (7U)
|
|
#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
|
|
|
|
/*! @name OBSERVE - USB OTG Observe register */
|
|
#define USB_OBSERVE_DMPD_MASK (0x10U)
|
|
#define USB_OBSERVE_DMPD_SHIFT (4U)
|
|
#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
|
|
#define USB_OBSERVE_DPPD_MASK (0x40U)
|
|
#define USB_OBSERVE_DPPD_SHIFT (6U)
|
|
#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
|
|
#define USB_OBSERVE_DPPU_MASK (0x80U)
|
|
#define USB_OBSERVE_DPPU_SHIFT (7U)
|
|
#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
|
|
|
|
/*! @name CONTROL - USB OTG Control register */
|
|
#define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U)
|
|
#define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U)
|
|
#define USB_CONTROL_DPPULLUPNONOTG(x) \
|
|
(((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
|
|
|
|
/*! @name USBTRC0 - USB Transceiver Control Register 0 */
|
|
#define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U)
|
|
#define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U)
|
|
#define USB_USBTRC0_USB_RESUME_INT(x) \
|
|
(((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
|
|
#define USB_USBTRC0_SYNC_DET_MASK (0x2U)
|
|
#define USB_USBTRC0_SYNC_DET_SHIFT (1U)
|
|
#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
|
|
#define USB_USBTRC0_USBRESMEN_MASK (0x20U)
|
|
#define USB_USBTRC0_USBRESMEN_SHIFT (5U)
|
|
#define USB_USBTRC0_USBRESMEN(x) \
|
|
(((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
|
|
#define USB_USBTRC0_USBRESET_MASK (0x80U)
|
|
#define USB_USBTRC0_USBRESET_SHIFT (7U)
|
|
#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
|
|
|
|
/*! @name USBFRMADJUST - Frame Adjust Register */
|
|
#define USB_USBFRMADJUST_ADJ_MASK (0xFFU)
|
|
#define USB_USBFRMADJUST_ADJ_SHIFT (0U)
|
|
#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group USB_Register_Masks */
|
|
|
|
/* USB - Peripheral instance base addresses */
|
|
/** Peripheral USB0 base address */
|
|
#define USB0_BASE (0x40072000u)
|
|
/** Peripheral USB0 base pointer */
|
|
#define USB0 ((USB_Type *)USB0_BASE)
|
|
/** Array initializer of USB peripheral base addresses */
|
|
#define USB_BASE_ADDRS \
|
|
{ USB0_BASE }
|
|
/** Array initializer of USB peripheral base pointers */
|
|
#define USB_BASE_PTRS \
|
|
{ USB0 }
|
|
/** Interrupt vectors for the USB peripheral type */
|
|
#define USB_IRQS \
|
|
{ USB0_IRQn }
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group USB_Peripheral_Access_Layer */
|
|
|
|
/*
|
|
** End of section using anonymous unions
|
|
*/
|
|
|
|
#if defined(__ARMCC_VERSION)
|
|
#pragma pop
|
|
#elif defined(__CWCC__)
|
|
#pragma pop
|
|
#elif defined(__GNUC__)
|
|
/* leave anonymous unions enabled */
|
|
#elif defined(__IAR_SYSTEMS_ICC__)
|
|
#pragma language = default
|
|
#else
|
|
#error Not supported compiler type
|
|
#endif
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group Peripheral_access_layer */
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
|
|
* @{
|
|
*/
|
|
|
|
#if defined(__ARMCC_VERSION)
|
|
#if (__ARMCC_VERSION >= 6010050)
|
|
#pragma clang system_header
|
|
#endif
|
|
#elif defined(__IAR_SYSTEMS_ICC__)
|
|
#pragma system_include
|
|
#endif
|
|
|
|
/**
|
|
* @brief Mask and left-shift a bit field value for use in a register bit range.
|
|
* @param field Name of the register bit field.
|
|
* @param value Value of the bit field.
|
|
* @return Masked and shifted value.
|
|
*/
|
|
#define NXP_VAL2FLD(field, value) (((value) << (field##_SHIFT)) & (field##_MASK))
|
|
/**
|
|
* @brief Mask and right-shift a register value to extract a bit field value.
|
|
* @param field Name of the register bit field.
|
|
* @param value Value of the register.
|
|
* @return Masked and shifted bit field value.
|
|
*/
|
|
#define NXP_FLD2VAL(field, value) (((value) & (field##_MASK)) >> (field##_SHIFT))
|
|
|
|
/*!
|
|
* @}
|
|
*/ /* end of group Bit_Field_Generic_Macros */
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- SDK Compatibility
|
|
---------------------------------------------------------------------------- */
|
|
|
|
/*!
|
|
* @addtogroup SDK_Compatibility_Symbols SDK Compatibility
|
|
* @{
|
|
*/
|
|
|
|
#define DMA_REQC_ARR_DMAC_MASK This_symbol_has_been_deprecated
|
|
#define DMA_REQC_ARR_DMAC_SHIFT This_symbol_has_been_deprecated
|
|
#define DMA_REQC_ARR_DMAC(x) This_symbol_has_been_deprecated
|
|
#define DMA_REQC_ARR_CFSM_MASK This_symbol_has_been_deprecated
|
|
#define DMA_REQC_ARR_CFSM_SHIFT This_symbol_has_been_deprecated
|
|
#define DMA_REQC0 This_symbol_has_been_deprecated
|
|
#define DMA_REQC1 This_symbol_has_been_deprecated
|
|
#define DMA_REQC2 This_symbol_has_been_deprecated
|
|
#define DMA_REQC3 This_symbol_has_been_deprecated
|
|
#define MCG_S_LOLS_MASK MCG_S_LOLS0_MASK
|
|
#define MCG_S_LOLS_SHIFT MCG_S_LOLS0_SHIFT
|
|
#define SIM_FCFG2_MAXADDR_MASK SIM_FCFG2_MAXADDR0_MASK
|
|
#define SIM_FCFG2_MAXADDR_SHIFT SIM_FCFG2_MAXADDR0_SHIFT
|
|
#define SIM_FCFG2_MAXADDR SIM_FCFG2_MAXADDR0
|
|
#define SPI_C2_SPLPIE_MASK This_symbol_has_been_deprecated
|
|
#define SPI_C2_SPLPIE_SHIFT This_symbol_has_been_deprecated
|
|
#define UART_C4_LBKDDMAS_MASK This_symbol_has_been_deprecated
|
|
#define UART_C4_LBKDDMAS_SHIFT This_symbol_has_been_deprecated
|
|
#define UART_C4_ILDMAS_MASK This_symbol_has_been_deprecated
|
|
#define UART_C4_ILDMAS_SHIFT This_symbol_has_been_deprecated
|
|
#define UART_C4_TCDMAS_MASK This_symbol_has_been_deprecated
|
|
#define UART_C4_TCDMAS_SHIFT This_symbol_has_been_deprecated
|
|
#define UARTLP_Type UART0_Type
|
|
#define UARTLP_BDH_REG UART0_BDH_REG
|
|
#define UARTLP_BDL_REG UART0_BDL_REG
|
|
#define UARTLP_C1_REG UART0_C1_REG
|
|
#define UARTLP_C2_REG UART0_C2_REG
|
|
#define UARTLP_S1_REG UART0_S1_REG
|
|
#define UARTLP_S2_REG UART0_S2_REG
|
|
#define UARTLP_C3_REG UART0_C3_REG
|
|
#define UARTLP_D_REG UART0_D_REG
|
|
#define UARTLP_MA1_REG UART0_MA1_REG
|
|
#define UARTLP_MA2_REG UART0_MA2_REG
|
|
#define UARTLP_C4_REG UART0_C4_REG
|
|
#define UARTLP_C5_REG UART0_C5_REG
|
|
#define UARTLP_BDH_SBR_MASK UART0_BDH_SBR_MASK
|
|
#define UARTLP_BDH_SBR_SHIFT UART0_BDH_SBR_SHIFT
|
|
#define UARTLP_BDH_SBR(x) UART0_BDH_SBR(x)
|
|
#define UARTLP_BDH_SBNS_MASK UART0_BDH_SBNS_MASK
|
|
#define UARTLP_BDH_SBNS_SHIFT UART0_BDH_SBNS_SHIFT
|
|
#define UARTLP_BDH_RXEDGIE_MASK UART0_BDH_RXEDGIE_MASK
|
|
#define UARTLP_BDH_RXEDGIE_SHIFT UART0_BDH_RXEDGIE_SHIFT
|
|
#define UARTLP_BDH_LBKDIE_MASK UART0_BDH_LBKDIE_MASK
|
|
#define UARTLP_BDH_LBKDIE_SHIFT UART0_BDH_LBKDIE_SHIFT
|
|
#define UARTLP_BDL_SBR_MASK UART0_BDL_SBR_MASK
|
|
#define UARTLP_BDL_SBR_SHIFT UART0_BDL_SBR_SHIFT
|
|
#define UARTLP_BDL_SBR(x) UART0_BDL_SBR(x)
|
|
#define UARTLP_C1_PT_MASK UART0_C1_PT_MASK
|
|
#define UARTLP_C1_PT_SHIFT UART0_C1_PT_SHIFT
|
|
#define UARTLP_C1_PE_MASK UART0_C1_PE_MASK
|
|
#define UARTLP_C1_PE_SHIFT UART0_C1_PE_SHIFT
|
|
#define UARTLP_C1_ILT_MASK UART0_C1_ILT_MASK
|
|
#define UARTLP_C1_ILT_SHIFT UART0_C1_ILT_SHIFT
|
|
#define UARTLP_C1_WAKE_MASK UART0_C1_WAKE_MASK
|
|
#define UARTLP_C1_WAKE_SHIFT UART0_C1_WAKE_SHIFT
|
|
#define UARTLP_C1_M_MASK UART0_C1_M_MASK
|
|
#define UARTLP_C1_M_SHIFT UART0_C1_M_SHIFT
|
|
#define UARTLP_C1_RSRC_MASK UART0_C1_RSRC_MASK
|
|
#define UARTLP_C1_RSRC_SHIFT UART0_C1_RSRC_SHIFT
|
|
#define UARTLP_C1_DOZEEN_MASK UART0_C1_DOZEEN_MASK
|
|
#define UARTLP_C1_DOZEEN_SHIFT UART0_C1_DOZEEN_SHIFT
|
|
#define UARTLP_C1_LOOPS_MASK UART0_C1_LOOPS_MASK
|
|
#define UARTLP_C1_LOOPS_SHIFT UART0_C1_LOOPS_SHIFT
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#define UARTLP_C2_SBK_MASK UART0_C2_SBK_MASK
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#define UARTLP_C2_SBK_SHIFT UART0_C2_SBK_SHIFT
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#define UARTLP_C2_RWU_MASK UART0_C2_RWU_MASK
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#define UARTLP_C2_RWU_SHIFT UART0_C2_RWU_SHIFT
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#define UARTLP_C2_RE_MASK UART0_C2_RE_MASK
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#define UARTLP_C2_RE_SHIFT UART0_C2_RE_SHIFT
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#define UARTLP_C2_TE_MASK UART0_C2_TE_MASK
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#define UARTLP_C2_TE_SHIFT UART0_C2_TE_SHIFT
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#define UARTLP_C2_ILIE_MASK UART0_C2_ILIE_MASK
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#define UARTLP_C2_ILIE_SHIFT UART0_C2_ILIE_SHIFT
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#define UARTLP_C2_RIE_MASK UART0_C2_RIE_MASK
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#define UARTLP_C2_RIE_SHIFT UART0_C2_RIE_SHIFT
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#define UARTLP_C2_TCIE_MASK UART0_C2_TCIE_MASK
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#define UARTLP_C2_TCIE_SHIFT UART0_C2_TCIE_SHIFT
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#define UARTLP_C2_TIE_MASK UART0_C2_TIE_MASK
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#define UARTLP_C2_TIE_SHIFT UART0_C2_TIE_SHIFT
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#define UARTLP_S1_PF_MASK UART0_S1_PF_MASK
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#define UARTLP_S1_PF_SHIFT UART0_S1_PF_SHIFT
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#define UARTLP_S1_FE_MASK UART0_S1_FE_MASK
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#define UARTLP_S1_FE_SHIFT UART0_S1_FE_SHIFT
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#define UARTLP_S1_NF_MASK UART0_S1_NF_MASK
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#define UARTLP_S1_NF_SHIFT UART0_S1_NF_SHIFT
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#define UARTLP_S1_OR_MASK UART0_S1_OR_MASK
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#define UARTLP_S1_OR_SHIFT UART0_S1_OR_SHIFT
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#define UARTLP_S1_IDLE_MASK UART0_S1_IDLE_MASK
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#define UARTLP_S1_IDLE_SHIFT UART0_S1_IDLE_SHIFT
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#define UARTLP_S1_RDRF_MASK UART0_S1_RDRF_MASK
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#define UARTLP_S1_RDRF_SHIFT UART0_S1_RDRF_SHIFT
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#define UARTLP_S1_TC_MASK UART0_S1_TC_MASK
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#define UARTLP_S1_TC_SHIFT UART0_S1_TC_SHIFT
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#define UARTLP_S1_TDRE_MASK UART0_S1_TDRE_MASK
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#define UARTLP_S1_TDRE_SHIFT UART0_S1_TDRE_SHIFT
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#define UARTLP_S2_RAF_MASK UART0_S2_RAF_MASK
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#define UARTLP_S2_RAF_SHIFT UART0_S2_RAF_SHIFT
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#define UARTLP_S2_LBKDE_MASK UART0_S2_LBKDE_MASK
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#define UARTLP_S2_LBKDE_SHIFT UART0_S2_LBKDE_SHIFT
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#define UARTLP_S2_BRK13_MASK UART0_S2_BRK13_MASK
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#define UARTLP_S2_BRK13_SHIFT UART0_S2_BRK13_SHIFT
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#define UARTLP_S2_RWUID_MASK UART0_S2_RWUID_MASK
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#define UARTLP_S2_RWUID_SHIFT UART0_S2_RWUID_SHIFT
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#define UARTLP_S2_RXINV_MASK UART0_S2_RXINV_MASK
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#define UARTLP_S2_RXINV_SHIFT UART0_S2_RXINV_SHIFT
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#define UARTLP_S2_MSBF_MASK UART0_S2_MSBF_MASK
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#define UARTLP_S2_MSBF_SHIFT UART0_S2_MSBF_SHIFT
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#define UARTLP_S2_RXEDGIF_MASK UART0_S2_RXEDGIF_MASK
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#define UARTLP_S2_RXEDGIF_SHIFT UART0_S2_RXEDGIF_SHIFT
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#define UARTLP_S2_LBKDIF_MASK UART0_S2_LBKDIF_MASK
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#define UARTLP_S2_LBKDIF_SHIFT UART0_S2_LBKDIF_SHIFT
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#define UARTLP_C3_PEIE_MASK UART0_C3_PEIE_MASK
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#define UARTLP_C3_PEIE_SHIFT UART0_C3_PEIE_SHIFT
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#define UARTLP_C3_FEIE_MASK UART0_C3_FEIE_MASK
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#define UARTLP_C3_FEIE_SHIFT UART0_C3_FEIE_SHIFT
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#define UARTLP_C3_NEIE_MASK UART0_C3_NEIE_MASK
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#define UARTLP_C3_NEIE_SHIFT UART0_C3_NEIE_SHIFT
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#define UARTLP_C3_ORIE_MASK UART0_C3_ORIE_MASK
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#define UARTLP_C3_ORIE_SHIFT UART0_C3_ORIE_SHIFT
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#define UARTLP_C3_TXINV_MASK UART0_C3_TXINV_MASK
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#define UARTLP_C3_TXINV_SHIFT UART0_C3_TXINV_SHIFT
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#define UARTLP_C3_TXDIR_MASK UART0_C3_TXDIR_MASK
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#define UARTLP_C3_TXDIR_SHIFT UART0_C3_TXDIR_SHIFT
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#define UARTLP_C3_R9T8_MASK UART0_C3_R9T8_MASK
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#define UARTLP_C3_R9T8_SHIFT UART0_C3_R9T8_SHIFT
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#define UARTLP_C3_R8T9_MASK UART0_C3_R8T9_MASK
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#define UARTLP_C3_R8T9_SHIFT UART0_C3_R8T9_SHIFT
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#define UARTLP_D_R0T0_MASK UART0_D_R0T0_MASK
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#define UARTLP_D_R0T0_SHIFT UART0_D_R0T0_SHIFT
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#define UARTLP_D_R1T1_MASK UART0_D_R1T1_MASK
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#define UARTLP_D_R1T1_SHIFT UART0_D_R1T1_SHIFT
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#define UARTLP_D_R2T2_MASK UART0_D_R2T2_MASK
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#define UARTLP_D_R2T2_SHIFT UART0_D_R2T2_SHIFT
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#define UARTLP_D_R3T3_MASK UART0_D_R3T3_MASK
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#define UARTLP_D_R3T3_SHIFT UART0_D_R3T3_SHIFT
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#define UARTLP_D_R4T4_MASK UART0_D_R4T4_MASK
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#define UARTLP_D_R4T4_SHIFT UART0_D_R4T4_SHIFT
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#define UARTLP_D_R5T5_MASK UART0_D_R5T5_MASK
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#define UARTLP_D_R5T5_SHIFT UART0_D_R5T5_SHIFT
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#define UARTLP_D_R6T6_MASK UART0_D_R6T6_MASK
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#define UARTLP_D_R6T6_SHIFT UART0_D_R6T6_SHIFT
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#define UARTLP_D_R7T7_MASK UART0_D_R7T7_MASK
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#define UARTLP_D_R7T7_SHIFT UART0_D_R7T7_SHIFT
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#define UARTLP_MA1_MA_MASK UART0_MA1_MA_MASK
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#define UARTLP_MA1_MA_SHIFT UART0_MA1_MA_SHIFT
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#define UARTLP_MA1_MA(x) UART0_MA1_MA(x)
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#define UARTLP_MA2_MA_MASK UART0_MA2_MA_MASK
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#define UARTLP_MA2_MA_SHIFT UART0_MA2_MA_SHIFT
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#define UARTLP_MA2_MA(x) UART0_MA2_MA(x)
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#define UARTLP_C4_OSR_MASK UART0_C4_OSR_MASK
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#define UARTLP_C4_OSR_SHIFT UART0_C4_OSR_SHIFT
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#define UARTLP_C4_OSR(x) UART0_C4_OSR(x)
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#define UARTLP_C4_M10_MASK UART0_C4_M10_MASK
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#define UARTLP_C4_M10_SHIFT UART0_C4_M10_SHIFT
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#define UARTLP_C4_MAEN2_MASK UART0_C4_MAEN2_MASK
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#define UARTLP_C4_MAEN2_SHIFT UART0_C4_MAEN2_SHIFT
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#define UARTLP_C4_MAEN1_MASK UART0_C4_MAEN1_MASK
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#define UARTLP_C4_MAEN1_SHIFT UART0_C4_MAEN1_SHIFT
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#define UARTLP_C5_RESYNCDIS_MASK UART0_C5_RESYNCDIS_MASK
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#define UARTLP_C5_RESYNCDIS_SHIFT UART0_C5_RESYNCDIS_SHIFT
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#define UARTLP_C5_BOTHEDGE_MASK UART0_C5_BOTHEDGE_MASK
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#define UARTLP_C5_BOTHEDGE_SHIFT UART0_C5_BOTHEDGE_SHIFT
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#define UARTLP_C5_RDMAE_MASK UART0_C5_RDMAE_MASK
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#define UARTLP_C5_RDMAE_SHIFT UART0_C5_RDMAE_SHIFT
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#define UARTLP_C5_TDMAE_MASK UART0_C5_TDMAE_MASK
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#define UARTLP_C5_TDMAE_SHIFT UART0_C5_TDMAE_SHIFT
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#define NV_FOPT_EZPORT_DIS_MASK This_symbol_has_been_deprecated
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#define NV_FOPT_EZPORT_DIS_SHIFT This_symbol_has_been_deprecated
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#define FPTA_BASE FGPIOA_BASE
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#define FPTA FGPIOA
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#define FPTB_BASE FGPIOB_BASE
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#define FPTB FGPIOB
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#define FPTC_BASE FGPIOC_BASE
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#define FPTC FGPIOC
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#define FPTD_BASE FGPIOD_BASE
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#define FPTD FGPIOD
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#define FPTE_BASE FGPIOE_BASE
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#define FPTE FGPIOE
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#define PTA_BASE GPIOA_BASE
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#define PTA GPIOA
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#define PTB_BASE GPIOB_BASE
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#define PTB GPIOB
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#define PTC_BASE GPIOC_BASE
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#define PTC GPIOC
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#define PTD_BASE GPIOD_BASE
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#define PTD GPIOD
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#define PTE_BASE GPIOE_BASE
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#define PTE GPIOE
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#define LPTimer_IRQn LPTMR0_IRQn
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#define LPTimer_IRQHandler LPTMR0_IRQHandler
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#define LLW_IRQn LLWU_IRQn
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#define LLW_IRQHandler LLWU_IRQHandler
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/*!
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* @}
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*/ /* end of group SDK_Compatibility_Symbols */
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#endif /* _MKL25Z4_H_ */
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